Rose Thompson
2491ef0e23
Fixed some more bugs in the Zicclsm signature.
2023-11-10 17:36:10 -06:00
Rose Thompson
3245e2a99e
Fixed bug in the Zicclsm test.
2023-11-10 17:34:23 -06:00
Rose Thompson
b555620ac8
Fixed bug in the misaligned access test.
2023-11-10 17:02:15 -06:00
Rose Thompson
4b24878053
Merge branch 'main' into Zicclsm
2023-11-10 16:15:32 -06:00
naichewa
7d88050ecd
fix hardware interlock, hold mode deassert
2023-11-08 15:20:51 -08:00
naichewa
fbeaad4150
fifo fixes and edge case testing
2023-11-07 17:59:46 -08:00
naichewa
6a148349de
added test cases
2023-11-02 15:43:08 -07:00
Rose Thompson
3e5aa77b5d
Merge branch 'main' into Zicclsm
2023-11-02 12:55:51 -05:00
Rose Thompson
f89673d7e5
Doesn't yet fully work.
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Thomas is going to finish debugging while I'm on the RISCV summit next week.
2023-11-02 12:07:42 -05:00
Rose Thompson
3817d792f6
Progress. I think the remaining bugs are in the regression test's signature.
2023-11-01 17:51:48 -05:00
naichewa
755c055f74
comments, more test cases
2023-11-01 01:26:34 -07:00
Rose Thompson
b5ecae2056
Working through issues with the psill logic.
2023-10-31 18:50:13 -05:00
Rose Thompson
53bcb45844
Progress
2023-10-31 14:50:33 -05:00
Rose Thompson
0dd516e90f
Fixed bugs in misaligned test.
2023-10-31 12:49:35 -05:00
Rose Thompson
6223e8382d
First stab at the misaligned test.
2023-10-31 12:30:10 -05:00
naichewa
3570468ef5
Merge branch 'main' into spi
2023-10-30 17:01:41 -07:00
naichewa
7a0fb9a193
hardware interlock
2023-10-30 17:00:20 -07:00
Rose Thompson
7e8d132ead
Updated mmu to not generate trap on cacheable misaligned access when supported.
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Updated tests with David's help.
2023-10-30 18:26:11 -05:00
David Harris
4d191e63cc
Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder.
2023-10-30 09:56:17 -07:00
Rose Thompson
e3154bb7a3
Updated comments in the cboz tests.
2023-10-20 15:15:47 -05:00
Rose Thompson
badfc1e4bb
Updated comments for the cbom tests.
2023-10-20 15:13:52 -05:00
naichewa
19e45a9182
Merge branch 'main' into spi
2023-10-16 22:59:50 -07:00
David Harris
1e2f1089ca
Incorporated new AMO tests from riscv-arch-test
2023-10-16 10:25:45 -07:00
David Harris
5f9b555b93
Added CSR permission tests for mconfigptr, menvcfg, mseccfg, etc.
2023-10-15 15:31:03 -07:00
David Harris
88745f9265
Added WALLY minfo test for rv32
2023-10-15 06:48:22 -07:00
David Harris
b8a17afd5d
minfo test working again with mconfigptr for RV64
2023-10-15 06:41:52 -07:00
naichewa
59afc3b92c
always working after reg bit swizzle changes
2023-10-13 14:22:32 -07:00
naichewa
dd3e701447
correct delay0, fmt register test entries
2023-10-12 15:13:23 -07:00
naichewa
1fa4ad90ec
transferred spi changes in ECA-authorized commit
2023-10-12 13:36:57 -07:00
David Harris
df7f2679d7
Added MENVCFG.HADE bit and updated SVADU to depend on this bit
2023-10-04 09:34:28 -07:00
Ross Thompson
4e20d08f0c
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-09-05 11:12:00 -05:00
David Harris
1ced158596
tlbNAPOT hangs due to PBMT making instruction memory uncacheable, and spill logic not working there. Fixed TLBLRU to update recently used on TLBHit rather than CAMHit. Moved coverage exclusions to proper line in pmachecker
2023-09-02 12:56:36 -07:00
David Harris
98fa3a78dd
Improved tlb and controller coverage; fixed exclusions on broken lines
2023-08-31 00:27:47 -07:00
David Harris
376ca68cbb
Improved NAPOT test coverage
2023-08-30 21:04:36 -07:00
Ross Thompson
047c2c43ac
Extended the CBOM test to cover a 4 way set associative cache with 4KiB ways.
2023-08-30 11:29:44 -05:00
David Harris
c27ec6830d
Initial TLB NAPOT tests
2023-08-29 12:39:24 -07:00
David Harris
10549b7787
Completed basic tests of svnapot and svpbmt
2023-08-28 06:57:35 -07:00
David Harris
847c0dd099
Merge pull request #393 from ross144/main
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Implemented and tested CBOZ instruction
2023-08-24 19:17:38 -07:00
David Harris
d12be1faac
Merge pull request #394 from harshinisrinath1001/main
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Improved testing of csri with priv.S!
2023-08-24 19:16:50 -07:00
harshinisrinath
49014e61bc
Improved testing of csri with priv.S
2023-08-24 18:39:15 -07:00
Ross Thompson
c114d3a07d
Added rv32 cboz test.
2023-08-24 17:02:53 -05:00
Ross Thompson
fbcf6be06d
Now have CBOZ instructions working!
2023-08-24 16:47:35 -05:00
Ross Thompson
92302331b7
Oups forgot to include the 32-bit cbom test in previous commit.
2023-08-24 09:04:41 -05:00
David Harris
38e437c724
Merge pull request #383 from ross144/main
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Adds Zicbom support for D-cache only. I-cache not yet supported. Tests 32 and 64 bit versions. Please rebuild regressions wally32 and wally64. To save rebuild time edit lines 11-12 of tests/riscof/Makefile
2023-08-21 13:32:00 -07:00
David Harris
fa49117521
Merge pull request #381 from harshinisrinath1001/main
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Tried to improve coverage of CSRI with priv.S
2023-08-21 13:28:39 -07:00
Ross Thompson
168ef0ab53
Have a working 32 bit cbom test!
2023-08-21 13:46:09 -05:00
Ross Thompson
6ffbdaac0a
Working CBO tests for 64 bit!
2023-08-21 12:55:07 -05:00
Ross Thompson
34a8c042b7
Made a bunch of progress towards getting cbo instructions tested.
2023-08-21 11:46:21 -05:00
harshinisrinath
37bfb5998f
cleared stimer interrupt
2023-08-20 15:42:27 -07:00
harshinisrinath
fce2023aa8
tried to improve testing of csri in privileged module
2023-08-20 15:40:02 -07:00
