Ross Thompson
6099b0e763
Fixed bugs in boot and new flash card merge. Works with arty a7 now.
2023-07-22 15:52:25 -05:00
Ross Thompson
3eeecd2f27
Merge branch 'boot' into mergeBoot
...
Merges Jacob's new sdc controller into wally.
2023-07-21 17:43:45 -05:00
Ross Thompson
0063665baf
Improved the critical path even more. The Arty A7 works upto 19Mhz easily. Testing out 22Mhz now.
2023-07-21 16:31:26 -05:00
Ross Thompson
37078f3d9b
Modified the LSU/IFU and caches to improve critical path. Arty A7 went from 15 to 17Mhz. I believe we can push all the way to 20+Mhz with relatively little effort. Along the way I'm fixing up the scripts build the linux images for the flash card.
2023-07-21 13:06:27 -05:00
Jacob Pease
36785848a5
Working new boot process. Buildroot package for sdc.
2023-07-20 14:15:59 -05:00
Ross Thompson
9ba3113e9c
Improved critical path.
2023-07-19 14:59:37 -05:00
Ross Thompson
936b2a8c8b
Optimized critial path in ifu's spill logic.
2023-07-19 14:13:46 -05:00
Ross Thompson
0e22fe5231
Removed QEMU from configurations.
2023-07-19 10:23:55 -05:00
Ross Thompson
3bf2b35704
Wow. The newest version of Vivado does not like the enums as parameters.
...
The solution is simple. I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers.
2023-07-18 15:07:10 -05:00
Ross Thompson
c7283f8c83
Merge branch 'main' of github.com:ross144/cvw
2023-07-17 15:52:27 -05:00
Ross Thompson
80093a0eb1
Updated the FPGA zero stage bootloader.
2023-07-17 15:52:13 -05:00
Ross Thompson
20751790f6
Fixed bug with performance counters not tracking the correct number of requested icache and dcache memory operations.
2023-07-14 16:31:44 -05:00
Jacob Pease
142ec857ed
Modified bootloader to access GUID partitions. SDC interrupt to PLIC.
...
Since writing an SD card image generation script, the bootloader
needed to be altered to access individual binaries from specific
partitions. A new file, gpt.c with it's header gpt.h, have been added
to the bootloader to facilitate this.
The SDC has been added to the device tree for the VCU108
board. Additionally the SDC interrupt signal was added to the PLIC
node in the device tree. The PLIC itself was modified to accept the
SDC interrupt signal.
2023-07-14 13:36:44 -05:00
David Harris
45667c9f4d
Clean up privilege rs1 decoding and implement svinval as sfence.vma
2023-07-13 02:41:17 -07:00
Ross Thompson
58dfc15844
Merge branch 'main' of github.com:ross144/cvw into main
2023-07-11 15:08:26 -05:00
Ross Thompson
c12bc4f435
Created separate temporary testbench for xcelium.
2023-07-11 15:07:33 -05:00
Ross Thompson
05b1cce2d1
RTL changes for Xcelium.
2023-07-11 10:51:02 -05:00
Ross Thompson
e647937b27
Fixed the privilege decoder bug which prevented the fpga linux boot.
2023-07-10 17:00:06 -05:00
Ross Thompson
47ee92d6e5
Merge pull request #359 from davidharrishmc/dev
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CSR updates
2023-07-10 13:16:57 -04:00
David Harris
c91bbc3ca8
MENVCFG only exists if U_SUPPORTED
2023-07-09 18:25:07 -07:00
Ross Thompson
4e54e5169b
Changes for xcelium.
2023-07-07 18:22:28 -05:00
Ross Thompson
40b2f7ff9c
Updated comments.
2023-07-06 15:24:26 -05:00
Ross Thompson
dc50ddd75e
Removed unused parameter.
2023-07-06 14:57:07 -05:00
Ross Thompson
0394f3232f
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-07-06 14:55:43 -05:00
David Harris
74a573cedd
Removed outdated commment about endianness
2023-07-06 12:41:46 -07:00
David Harris
29e62f05a4
Removed MTINST, which is not used in a system without a hypervisor
2023-07-06 12:40:53 -07:00
Ross Thompson
18278b7f4d
It's a bit hacky, but the plic now passes the regression test and should be compatible with the fpga.
2023-07-06 14:07:37 -05:00
Ross Thompson
ba9d5287d9
This is at least functionally correct, but has verilator lint issues.
2023-07-06 11:53:34 -05:00
Ross Thompson
930aed0898
closer, but the wally32/64priv tests are failing.
2023-07-05 17:47:38 -05:00
Ross Thompson
c0fdd3fbca
Partially solved fpga boot.
2023-07-05 17:30:55 -05:00
David Harris
19efc4eda8
Fixed comment typo
2023-07-04 11:34:58 -07:00
David Harris
4f07d89d74
fixed spacing in fdivsqrt
2023-07-04 11:27:36 -07:00
David Harris
e6ba362794
Added prefetch instructions; sent cbo instructions to LSU
2023-07-02 10:55:35 -07:00
David Harris
cc87317189
Added prefetch signals
2023-07-02 10:06:58 -07:00
David Harris
a5c6ae1f78
Enhanced decoder to produce individual CMOpE output for the 4 CMO instructions
2023-07-02 09:35:05 -07:00
David Harris
6a88ac28e4
Fixed csr typos
2023-07-02 02:01:40 -07:00
David Harris
96477a4879
Fixed ENVCFG to reply on both MENVCFG and SENVCFG when in user mode
2023-07-02 02:00:27 -07:00
David Harris
e2708534cd
Added environment configuration control (menvcfg/senvcfg) of cbo instructions
2023-07-02 01:52:25 -07:00
David Harris
4d1ddd0c91
Gated floating-point load/stores with STATUS_FS and added initial decoding for Cache Management Operations
2023-07-02 00:34:30 -07:00
David Harris
110dd42cfb
improved decoder checking atomic and RW and MW and privileged instructions
2023-07-02 00:02:03 -07:00
David Harris
07cf1dd9da
improved decoder checking atomic instructions
2023-07-01 23:10:57 -07:00
David Harris
e05288afd9
Improved instruction decoding for illegal floating-point loads/stores and fences
2023-07-01 22:48:04 -07:00
Ross Thompson
1d2eb60ffb
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-06-18 16:37:19 -05:00
David Harris
95960620a2
Removed redundant and not-covered atomic check from StoreStallD
2023-06-16 16:05:53 -07:00
Ross Thompson
2f35bec970
FPGA synthesis is broken. This commit moves closer to fixing the issues causes by parameterization.
2023-06-16 15:40:13 -05:00
Ross Thompson
6d31936e89
Added comment to uart LCR to check reset value after updating FPGA.
2023-06-15 15:39:51 -05:00
Ross Thompson
34d1d50b87
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-06-15 15:38:38 -05:00
Ross Thompson
a011b7d591
Merge branch 'testbench-params2'
2023-06-15 15:31:13 -05:00
Ross Thompson
a55bcad5c1
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-06-15 14:57:23 -05:00
David Harris
52ab586a9d
Added input gating on FPU
2023-06-15 12:38:33 -07:00
