Rose Thompson
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21b2a71bd6
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Updates to btb logger processing.
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2023-11-15 16:53:44 -06:00 |
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Rose Thompson
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c4f4e0fbc0
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Added btb reference data.
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2023-11-15 16:39:35 -06:00 |
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Rose Thompson
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9a90c15f37
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Extended SeparateBranch to support both just branches and all control flow instructions.
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2023-11-15 16:36:49 -06:00 |
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Rose Thompson
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bc935b1b3b
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Fixed second bug in the logger script when branch logging enabled but counter logger not.
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2023-11-15 14:56:02 -06:00 |
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Rose Thompson
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5d4a89b27c
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Fixed bug in the btb branch logging.
We were only logging branch instructions not all control flow instructions which dramatically skewed the results for sim_bp.
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2023-11-15 14:51:47 -06:00 |
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Rose Thompson
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feb45b9b59
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Patched up linux imperas testbench.
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2023-11-14 14:20:13 -06:00 |
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Rose Thompson
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65356e362a
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Merge branch 'main' of github.com:ross144/cvw
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2023-11-14 13:54:48 -06:00 |
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Rose Thompson
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1c54a5698b
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Modified the device trees to include all the minor extensions.
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2023-11-14 13:54:16 -06:00 |
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Rose Thompson
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efc1d732d8
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Fixed the imperas testbench to be compatible with the config changes.
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2023-11-14 12:57:44 -06:00 |
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Rose Thompson
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fdb75203cb
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Added cbop to to rv32gc.
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2023-11-14 10:55:22 -06:00 |
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Rose Thompson
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d4bc9da085
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Fixed another bug in the updated script changes.
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2023-11-13 18:12:02 -06:00 |
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Rose Thompson
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919b7cccf1
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Merge branch 'main' of github.com:ross144/cvw
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2023-11-13 18:10:35 -06:00 |
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Rose Thompson
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f8b65f50b0
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Fixed bugs in the updated fpga synthe script.
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2023-11-13 18:10:22 -06:00 |
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Rose Thompson
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05eb5460b4
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Removed fpga config. No longer needed.
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2023-11-13 17:50:29 -06:00 |
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Rose Thompson
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d5f0c15b90
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Modified the fpga build script to generate it's own config file rather than use the one in config/fpga.
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2023-11-13 17:48:28 -06:00 |
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Rose Thompson
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95fc5f4a1c
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Towards removing the FPGA config file.
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2023-11-13 17:20:26 -06:00 |
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Rose Thompson
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6b7ff50a84
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Reduced Arty A7 clock speed to 20Mhz to support Zicclsm.
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2023-11-13 16:44:02 -06:00 |
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Rose Thompson
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a6995af91c
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Fixed bug in uncore updates which broke SDC.
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2023-11-13 16:15:23 -06:00 |
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Rose Thompson
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707b0c557c
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Cleanup and optimization of Zicclsm.
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2023-11-13 14:28:22 -06:00 |
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Rose Thompson
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da59cb71a9
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Commented out the arch64priv misaligned load/store tests since we added Zicclsm to the rv64gc config.
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2023-11-13 14:12:27 -06:00 |
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Rose Thompson
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540d8d930d
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Cleanup.
Linux makefile
wally tracer. probably reduce some complexity here.
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2023-11-13 14:04:43 -06:00 |
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Rose Thompson
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1f7d91e8e0
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Merge branch 'Zicclsm'
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2023-11-13 13:53:42 -06:00 |
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Rose Thompson
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55bcc4dbc1
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Updates to linux config files for sdc.
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2023-11-13 13:53:23 -06:00 |
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Rose Thompson
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13908ac41c
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Updated buildroot to use kernel 6.6 and added dedicated qemu emulation script.
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2023-11-13 12:36:32 -06:00 |
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Rose Thompson
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cc7a0b211a
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Cleanup.
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2023-11-13 12:35:11 -06:00 |
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Rose Thompson
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c8cca8dfb8
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Simplification.
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2023-11-10 18:39:36 -06:00 |
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Rose Thompson
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9dfe421c55
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Yay! Zicclsm passes my regression test now.
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2023-11-10 18:28:51 -06:00 |
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Rose Thompson
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c0e02ae190
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Found another bug in the RTL's Zicclsm alignment.
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2023-11-10 18:26:55 -06:00 |
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Rose Thompson
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02ab9fe99c
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Fixed all the bugs associated with the signature and the store side of misaligned access. Load misaligned is still causing some issues.
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2023-11-10 17:58:42 -06:00 |
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Rose Thompson
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bd866e1025
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Fixed some more bugs in the Zicclsm signature.
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2023-11-10 17:36:10 -06:00 |
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Rose Thompson
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efecb0c346
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Fixed bug in the Zicclsm test.
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2023-11-10 17:34:23 -06:00 |
|
Rose Thompson
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84d86b1994
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Fixed spill bugs in the aligner.
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2023-11-10 17:18:45 -06:00 |
|
Rose Thompson
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ada354f443
|
Fixed bug in the misaligned access test.
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2023-11-10 17:02:15 -06:00 |
|
Rose Thompson
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b74bfbeefd
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Merge branch 'main' into Zicclsm
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2023-11-10 16:15:32 -06:00 |
|
Rose Thompson
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baacb6f6eb
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Missed tests.vh.
|
2023-11-10 16:10:10 -06:00 |
|
Rose Thompson
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9abd26aad9
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Fixed bug which broke the non Zicclsm configs.
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2023-11-10 16:08:04 -06:00 |
|
Rose Thompson
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e1a7c7986a
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Merge pull request #463 from davidharrishmc/dev
Dev
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2023-11-10 08:48:07 -08:00 |
|
David Harris
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426aabbc1a
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Imperas commenting
|
2023-11-10 08:26:32 -08:00 |
|
David Harris
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7e00581187
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Add Svadu support and SPI to imperas configuration
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2023-11-10 06:27:25 -08:00 |
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David Harris
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d7ced56c60
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Merge pull request #460 from naichewa/main
removed vestigial logic, added comments, deleted unused signals
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2023-11-10 05:18:57 -08:00 |
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naichewa
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5ce16dcb63
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Cleanup
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2023-11-09 16:52:55 -08:00 |
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naichewa
|
3052a68d84
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Remove old 2/4 bit logic, add comments,
clean up unused signals
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2023-11-09 16:48:11 -08:00 |
|
David Harris
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bae3772548
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-11-09 10:33:25 -08:00 |
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Rose Thompson
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1d2eccc14d
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Merge pull request #458 from stineje/main
fix to setup.csh and also ppaSynth.py
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2023-11-09 10:20:05 -08:00 |
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David Harris
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625652b9ca
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Reporting stall path in synthesis script, support Zcb in Imperas
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2023-11-09 06:59:29 -08:00 |
|
James E. Stine
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9a47667fd7
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update README on ppa
|
2023-11-09 01:00:33 -06:00 |
|
James E. Stine
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5a115bc6f2
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update ppaSynth.py with runCommand
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2023-11-09 00:52:40 -06:00 |
|
James E. Stine
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a6bc69d73f
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Add encoding for utf-8 on wrapperGen.py to avoid issue with incorrect encoding on RHEL C-shell
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2023-11-08 23:57:59 -06:00 |
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David Harris
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32f68ac4e5
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-11-08 16:06:50 -08:00 |
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David Harris
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0e1b4bf8f6
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Merge pull request #459 from naichewa/main
hardware interlock and hold mode fixes
|
2023-11-08 16:06:39 -08:00 |
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