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Author	SHA1	Message	Date
Rose Thompson	1588881a8c	Merge pull request #897 from JacobPease/main ... New bootloader: Uses SPI to interface with SD card	2024-08-06 17:46:51 -05:00
Jacob Pease	2dc7e0f76f	Added and extra header and changed the comments to be accurate in ram1p1rwbe.sv	2024-08-06 17:36:42 -05:00
Jacob Pease	280b5baa59	Added header to new bootloader files.	2024-08-06 17:28:50 -05:00
Jacob Pease	954e21148f	Removed line referring to local file in wally.tcl.	2024-08-06 17:11:08 -05:00
Jacob Pease	af2344d2d5	Merge branch 'main' of github.com:openhwgroup/cvw into spiboot	2024-08-06 17:09:39 -05:00
Jacob Pease	665396fdb3	SD card is now mountable on the fpga. The relevant files have been added. The most important changes are in the buildroot linux configuration and device tree.	2024-08-06 16:57:57 -05:00
Jacob Pease	ad9c98c19c	Added file necessary to split boot.mem into boot.mem and data.mem.	2024-08-02 15:36:06 -05:00
Jacob Pease	83b0a83d5c	Removed HSELEXTSDC and fixed SD card pin definitions.	2024-08-02 15:35:18 -05:00
Jacob Pease	11a057b0b3	Updated wally source files for zsbl testing.	2024-08-02 15:33:57 -05:00
Jacob Pease	1e20d5aea6	Added preload pointing to data.mem in ram1p1rwbe.sv	2024-08-02 15:21:15 -05:00
Jacob Pease	897f6561cd	New bootloader now works. Added special print functions and print messages. sdclk is set to 3MHz after initialization currently.	2024-08-02 15:19:52 -05:00
Jacob Pease	fcd88d6e6f	Added functions to read registers and print information on failure. Also added a getTime function for a pretty boot display.	2024-08-02 15:14:30 -05:00
Jacob Pease	38071d8267	Updated formatting of gpt.c and boot.c.	2024-07-31 11:12:05 -05:00
Jacob Pease	ee980e39f3	Added function to set SPI clock speed.	2024-07-31 11:00:44 -05:00
Jacob Pease	c4ae17c679	Cleaned up code formatting a bit and added ability to set the SD card clock speed.	2024-07-31 10:59:41 -05:00
Jacob Pease	a263f836f2	Added extra UART macros and functions for code readability and the ability to print decimal numbers.	2024-07-31 10:58:15 -05:00
Jacob Pease	3975f60299	Added carriage returns to line feed characters. UART messages print properly now.	2024-07-25 13:05:57 -05:00
Jacob Pease	a36e846b02	Changed formatting and added new UART divsor calculation from OpenSBI.	2024-07-25 13:04:27 -05:00
Rose Thompson	6f78a60468	Merge pull request #896 from davidharrishmc/dev ... Updated ImperasTG derived config to turn off peripherals	2024-07-25 12:20:31 -05:00
David Harris	da853b45e6	Updated ImperasTG derived config to turn off peripherals	2024-07-25 10:08:34 -07:00
Rose Thompson	6496454054	Merge pull request #895 from davidharrishmc/dev ... Fix Issue 894 about floating-point decoding of reserved rm/frm	2024-07-25 11:51:32 -05:00
David Harris	faa1378920	Legalized PMPconfig WARL	2024-07-25 09:43:54 -07:00
David Harris	d5af25ffbf	CHeck legal rnum field when decoding aes64ks1i	2024-07-25 09:19:23 -07:00
Jacob Pease	336a413f31	Added ability to split boot.memfile into boot.mem and data.mem.	2024-07-25 11:19:15 -05:00
David Harris	5bf7250687	Issue #894: trap on floating-point ops with reserved rounding modes: detect Zfa flt	2024-07-25 09:09:13 -07:00
David Harris	f7dd49cc6c	Issue #894: trap on floating-point ops with reserved rounding modes	2024-07-25 06:59:58 -07:00
Jacob Pease	0dae881a0d	Fixed SDCCLK name discrepency.	2024-07-24 22:48:31 -05:00
Jacob Pease	ebdf25a53b	Commented out references to old axi IP from wally.tcl.	2024-07-24 22:47:15 -05:00
Jacob Pease	2caf9e93be	Removed old axi IP from fpga Makefile. Added sed for data.mem file loaded into uncore ram.	2024-07-24 22:46:24 -05:00
Jacob Pease	d15be492cb	Masked lower byte when writing to DLL.	2024-07-24 22:44:27 -05:00
Jacob Pease	286d80de7e	Initialized UART with Arty frequency and baud rate. Will make this dynamic in the future	2024-07-24 22:43:47 -05:00
Jacob Pease	0107a400d1	Added uart header to gpt.c.	2024-07-24 22:43:16 -05:00
David Harris	2c7bc7038e	Merge pull request #892 from ross144/main ... Adds synthesizable RVVI FPGA hardware	2024-07-24 12:21:36 -07:00
Rose Thompson	ce61429bdf	Fixed the reset bug in wallyTracer.	2024-07-24 13:32:46 -05:00
Rose Thompson	5cae55561e	Removed unused file.	2024-07-24 13:30:25 -05:00
Rose Thompson	df88939bcb	Merge branch 'main' of https://github.com/openhwgroup/cvw	2024-07-24 13:14:25 -05:00
Rose Thompson	d0a5b278b7	Factored out the rvvi testbench code into rvvitbwrapper.	2024-07-24 13:10:57 -05:00
Rose Thompson	b1a711ae0f	Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim.	2024-07-24 12:47:50 -05:00
Rose Thompson	27f89fcdbd	Updated verilog-ethernet to remove all verilator warnings or at least suppress them.	2024-07-24 10:13:03 -05:00
Rose Thompson	9404a339ee	Handled all remaining verilator warnings in the rvvi synth code. Now it's time to take on the verilog-ethernet warnings.	2024-07-23 17:44:37 -05:00
Rose Thompson	6c212ebf0e	Changes are confirmed to work on the FPGA.	2024-07-23 17:39:38 -05:00
Jacob Pease	f1cc7dd5a3	Fixed verilog bugs.	2024-07-23 17:26:39 -05:00
Jacob Pease	dcb2edf888	Fixed syntax bugs. inline functions are now static and in the spi.h header.	2024-07-23 17:00:32 -05:00
Rose Thompson	e8e71ad643	Code cleanup.	2024-07-23 16:35:05 -05:00
Jacob Pease	5f0addd69a	Initial pass on SPI based bootloader code finished.	2024-07-23 16:33:49 -05:00
Jacob Pease	a8b9e7776b	Added some minor error checking to gpt.c.	2024-07-23 16:32:52 -05:00
Jacob Pease	ab00ea5a5c	Added sd_read64 to help with block reads and crc checking.	2024-07-23 16:32:29 -05:00
Rose Thompson	57ea39d685	Fixed rvvi csr counting.	2024-07-23 16:22:23 -05:00
Rose Thompson	54e0289608	Fixed bugs in the rvvi synth logic which encoded csr instructions.	2024-07-23 16:16:11 -05:00
Jacob Pease	57eeba5c8c	Progress made on implementing new disk read function.	2024-07-23 15:47:23 -05:00