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Author	SHA1	Message	Date
David Harris	d1a7832dd9	added comment about RAMs in cacheway	2022-07-10 12:47:34 +00:00
David Harris	f6a22e19b6	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-10 03:18:30 +00:00
Madeleine Masser-Frye	9bb01bc6f4	improved command line synth functionality	2022-07-09 04:51:23 +00:00
Madeleine Masser-Frye	e33ab9e515	explanations and modifications for general ppa use	2022-07-09 03:24:47 +00:00
Madeleine Masser-Frye	6f42b88d73	syntheses now write alib in their own directories	2022-07-09 02:40:41 +00:00
Katherine Parry	62205ebb3b	renamed FLoad2 to FStore2	2022-07-09 00:26:45 +00:00
Katherine Parry	97e7e619d9	moved fpu ieu write data mux to lsu	2022-07-08 23:56:57 +00:00
Madeleine Masser-Frye	5e6fcb6ea0	remove outdated scripts	2022-07-08 22:52:53 +00:00
Madeleine Masser-Frye	7517befbdd	tweaks to run synth without error	2022-07-08 22:52:10 +00:00
Madeleine Masser-Frye	8004712c75	cleaned up old commands and commented	2022-07-08 22:39:53 +00:00
Madeleine Masser-Frye	6f5ff93169	condensed cleanup, changed bpred_size to 4, moved synth hdl into own directory	2022-07-08 22:29:18 +00:00
Madeleine Masser-Frye	19b4d51d9c	told dc to look in synth directory for hdl and WORK	2022-07-08 22:16:34 +00:00
David Harris	4f8f154ad6	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-08 22:00:53 +00:00
David Harris	42e18e9a21	CoreMark makefile and printing improvements	2022-07-08 22:00:50 +00:00
cturek	0dc30a0acf	F Selection	2022-07-08 21:53:52 +00:00
DTowersM	5c14c97e49	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into HEAD	2022-07-08 21:25:58 +00:00
DTowersM	55e1bd6c77	added PORT_CFLAGS and some WIP 32bit support	2022-07-08 21:25:52 +00:00
Madeleine Masser-Frye	c4c6512c7f	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-08 20:42:04 +00:00
Madeleine Masser-Frye	510b3f33cb	made parallel synthesis in python command line based	2022-07-08 20:41:59 +00:00
Katherine Parry	c56fdd7e0f	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-07-08 12:30:50 -07:00
Katherine Parry	88b4f9b40a	renamed signals in cvt and prostproc	2022-07-08 12:30:43 -07:00
James Stine	99fed5d59f	Update SRAM to /proj/wally	2022-07-08 08:09:55 -05:00
slmnemo	e190aeb14b	Fixed error in gpio test	2022-07-08 02:27:16 -07:00
David Harris	8be1dafbd6	Removed testbench code that ignores mismatch on zero signatures	2022-07-08 09:17:31 +00:00
David Harris	87ea95e6c5	erge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-08 09:09:07 +00:00
David Harris	5ae88dbef0	Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc	2022-07-08 09:09:02 +00:00
David Harris	96cc66d151	Adjusting byte writes to RAM	2022-07-08 08:45:21 +00:00
David Harris	38ef8eebbb	Removed subwordwrite mention in cache because sww is needed to replicate data across byte enables	2022-07-08 08:44:37 +00:00
David Harris	234175f236	Removed unused swbytemask from CLINT	2022-07-08 08:43:24 +00:00
Madeleine Masser-Frye	5608cf327a	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-08 08:02:19 +00:00
Madeleine Masser-Frye	b37c0adab6	made wally synth flow shell based	2022-07-08 08:02:11 +00:00
Madeleine Masser-Frye	152c9fa0f3	restore flatten	2022-07-08 08:01:10 +00:00
David Harris	eba518625d	makefile	2022-07-07 16:43:03 -07:00
David Harris	7ef87777c1	CoreMark makefile tuning	2022-07-07 16:42:30 -07:00
Katherine Parry	b67792086c	moved unsused division code again	2022-07-07 16:41:26 -07:00
cturek	ccc97d6fee	Sqrt exponents	2022-07-07 23:34:56 +00:00
Katherine Parry	2e772dee69	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-07-07 16:29:44 -07:00
Katherine Parry	b1e2a1e5a1	Revert "moved old divsqrt to unusedsrc" ... This reverts commit 5dd07c76bd.	2022-07-07 16:29:17 -07:00
DTowersM	4786fb9fd6	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into HEAD	2022-07-07 23:11:35 +00:00
DTowersM	aa8580b2dc	new slim benchmarks/coremark directory now works on addins/coremark repo, removed old riscv-coremark directory	2022-07-07 23:11:02 +00:00
Katherine Parry	5dd07c76bd	moved old divsqrt to unusedsrc	2022-07-07 16:09:56 -07:00
Katherine Parry	75a8cea4e4	srt divider merged into fpu	2022-07-07 16:01:33 -07:00
cturek	010ab2e90e	Seventeen Square Root Tests	2022-07-07 22:48:46 +00:00
David Harris	425fec0f41	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-07 22:00:59 +00:00
Katherine Parry	c581fba4aa	modified wally shared	2022-07-07 21:59:43 +00:00
David Harris	f865994ba1	fixing port errors	2022-07-07 21:57:10 +00:00
Katherine Parry	7771f7b3eb	added load and store test	2022-07-07 21:48:51 +00:00
cturek	269884b672	Preprocessing for square root	2022-07-07 21:23:30 +00:00
David Harris	f2915129ab	Preliminary SRAM integration	2022-07-07 19:56:20 +00:00
Madeleine Masser-Frye	c7b03978bf	plot tuning, fo4 axis	2022-07-07 16:44:02 +00:00