Ross Thompson
13034c7406
Fixed bug in the two bit sat counter branch predictor. The SRAM needs to be read enabled by StallF.
2021-05-24 23:24:54 -05:00
Ross Thompson
dd26b754eb
Fixed minor bug in instruction class decoding.
2021-05-24 13:41:14 -05:00
Ross Thompson
b06fda88ff
Fixed bug with instruction classification. The class decoder was incorretly labeling jalr acting as both jalr and jr (no link).
2021-05-24 12:37:16 -05:00
Ross Thompson
2aa4db470b
Fixed synthesis bug with icache valid bit.
2021-05-04 13:03:08 -05:00
Ross Thompson
87d3869a6e
Fixed icache pcmux control for handling miss spill miss.
2021-05-04 11:05:01 -05:00
Ross Thompson
ed4f2ecb24
fixed subtle typo in icache fsm. Was messing up hit spill hit.
...
I believe the mibench qsort benchmark runs after this icache fix.
2021-05-03 16:55:36 -05:00
Ross Thompson
e09ac73eaf
Removed combinational loops between icache and PMA checker.
2021-05-03 14:51:25 -05:00
Ross Thompson
7185905f7b
Reduced icache to 1 port memory.
2021-05-03 14:47:49 -05:00
Ross Thompson
12b978fec2
Eliminated extra register and fixed ports to icache.
...
Still need to support physical tag check and write in icache memory.
Still need to reduce to 1 port SRAM in icache.
I would like to refactor the icache code.
2021-05-03 12:04:54 -05:00
Ross Thompson
b57c187208
Fixed typo in ifu for bypassing branch predictor.
...
Fixed missing signal name in local history predictor.
2021-05-03 08:56:45 -05:00
Jarred Allen
000f48cd75
Fix compile error in branch predictor
2021-04-29 14:36:56 -04:00
Shreya Sanghai
b554dc8e72
fixed bug in gshare, global and local history BP
2021-04-29 06:14:32 -04:00
Ross Thompson
14a69c1d06
Added the ability to exclude branch predictor.
2021-04-26 14:27:42 -05:00
Ross Thompson
a7e4d39ea1
Fixed issue with not saving the first cache block read on a miss spill.
2021-04-26 12:57:34 -05:00
bbracker
f921886451
merge cleanup; mem init is broken
2021-04-26 08:00:17 -04:00
bbracker
7947858481
it says I need to merge in order to pull
2021-04-26 07:46:24 -04:00
bbracker
8d77012995
progress on bus and lrsc
2021-04-26 07:43:16 -04:00
Ross Thompson
9e40fb072c
Merge branch 'tests' into icache-almost-working
2021-04-25 21:25:36 -05:00
Ross Thompson
c9bdaceddb
Fixed icache for 32 bit.
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Merge branch 'cache' into main
2021-04-22 16:45:29 -05:00
Ross Thompson
7c8d2e9b78
Partially working icache.
...
The current issue is a StallF is required to halt the icache from getting an updated PCF. However
if the dmemory is the reason for a stall it is possible for the icache stall to hold the d memory request continuously causing d memory to repeatedly read from memory. This keeps StallF high and
the icache FSM is never allowed to complete.
2021-04-22 10:20:36 -05:00
Thomas Fleming
88bd151d55
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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Conflicts:
wally-pipelined/src/ifu/ifu.sv
2021-04-21 20:01:08 -04:00
Thomas Fleming
70c801331a
Implement virtual memory protection
2021-04-21 19:58:36 -04:00
Ross Thompson
50e893eec9
Fixed for the instruction spills.
2021-04-21 16:47:05 -05:00
Teo Ene
008b308b79
Fixed most relevant remaining synthesis compilation warnings with Ben
2021-04-21 16:06:27 -05:00
Ross Thompson
269ea7997c
major progress.
...
It's running the icache is imperas tests now.
Compressed does not work yet.
2021-04-21 08:39:54 -05:00
Ross Thompson
a861a37b72
Why was the linter messed up?
...
There are a number of combo loops which need fixing outside the icache. They may be fixed in main.
We get to instruction address 50 now!
2021-04-20 22:06:12 -05:00
Ross Thompson
daa1ab9261
Progress on icache. Fixed some issues aligning the PC with instruction. Still broken.
2021-04-20 21:19:53 -05:00
Ross Thompson
649589ee2c
Broken icache. Design is done. Time to debug.
2021-04-20 19:55:49 -05:00
Jarred Allen
59b340dac9
Merge branch 'main' into cache
2021-04-19 00:05:23 -04:00
Thomas Fleming
2c4682c4be
Connect tlb and icache properly
2021-04-15 14:48:39 -04:00
Jarred Allen
7b4b1a31ef
Merge branch 'main' into cache
2021-04-15 13:47:19 -04:00
Shreya Sanghai
75caa65df1
Cherry Pick merge of Shreya's localhistory predictor changes into main.
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fixed minor bugs in localHistory
2021-04-15 09:04:36 -05:00
ShreyaSanghai
80fbd66113
added localHistoryPredictor
2021-04-15 08:58:22 -05:00
Shreya Sanghai
3696bf4f2c
fixed bugs in global history to read latest GHRE
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Cherry pick Shreya's commits into main branch.
2021-04-15 08:55:22 -05:00
Jarred Allen
4d58f673b2
Add a comment to explain a detail
2021-04-14 23:14:59 -04:00
Jarred Allen
c32fe09056
More icache bugfixes
2021-04-14 19:03:33 -04:00
Teo Ene
0bffac2c74
Various code syntax changes to bring HDL to a synthesizable level
2021-04-13 11:27:12 -05:00
Jarred Allen
357aed75ee
A few more cache fixes
2021-04-13 01:07:40 -04:00
Jarred Allen
6ce4d44ae1
Merge from branch 'main'
2021-04-08 17:19:34 -04:00
Thomas Fleming
e807f5d771
Implement support for superpages
2021-04-08 02:44:59 -04:00
Ross Thompson
d901cfc848
Merge branch 'icache_bp_bug' into tests
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Not sure this merge is right.
2021-04-06 21:46:40 -05:00
Ross Thompson
a5dc175ab2
Merge remote-tracking branch 'refs/remotes/origin/tests' into tests
2021-04-06 21:20:55 -05:00
Jarred Allen
4da2688c40
Fix another bug in icache
2021-04-06 17:47:00 -04:00
Jarred Allen
ecb2bc8163
Fix another bug in icache
2021-04-06 12:48:42 -04:00
Jarred Allen
4ebc991a65
Fix bug in icache
2021-04-03 18:10:54 -04:00
Thomas Fleming
f9bf2fbc01
Implement sfence.vma and fix tlb writing
2021-04-01 15:55:05 -04:00
Shreya Sanghai
bf3f4ff5b2
fixed minor bugs in localHistory
2021-04-01 13:40:08 -04:00
ShreyaSanghai
e33007e30e
added localHistoryPredictor
2021-04-01 22:22:40 +05:30
Shreya Sanghai
65e9747752
fixed bugs in global history to read latest GHRE
2021-03-31 21:56:14 -04:00
Ross Thompson
f1107c5d7b
Corrected a number of bugs in the branch predictor.
...
Added performance counters to individually track
branches; jumps, jump register, jal, and jalr; return.
jump and jump register are special cases of jal and jalr.
Similarlly return is a special case of jalr.
Also added counters to track if the branch direction was wrong,
btb target wrong, or the ras target was wrong.
Finally added one more counter to track if the BP incorrectly predicts
a non-cfi instruction.
2021-03-31 11:54:02 -05:00
