Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity
4,055 Commits 5 Branches 2 Tags 53 MiB
1226b2889e
Commit Graph

4055 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Domenico Ottolia
84911e6345 Fix 32 bit privileged tests!!! 2021-05-04 00:16:19 -04:00
Thomas Fleming
4f5ef65aeb Restore original order of tests 2021-05-03 23:50:21 -04:00
Thomas Fleming
d53afc8510 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-03 23:15:39 -04:00
Thomas Fleming
1f6db293fa Enable mmu tests in testbench 2021-05-03 23:15:23 -04:00
Domenico Ottolia
a7e89f43c1 Fix bug with IllegalInstrFaultM not getting correct value 2021-05-03 22:48:03 -04:00
Domenico Ottolia
12d8ff617b Run all tests 2021-05-03 22:38:59 -04:00
Domenico Ottolia
353d4e9238 Update cause tests to be longer 2021-05-03 22:38:26 -04:00
Domenico Ottolia
db4e447a25 Add mtvec and stvec tests to testbench 2021-05-03 22:19:50 -04:00
Shriya Nadgauda
c10d332c6e working testbench-imperas 2021-05-03 22:16:58 -04:00
Shriya Nadgauda
0be6b81df9 finishing merge conflict changes 2021-05-03 22:15:05 -04:00
Shriya Nadgauda
52e0b703b7 merge conflict fixes 2021-05-03 22:12:30 -04:00
Shriya Nadgauda
0282aebec7 updated pipeline tests 2021-05-03 22:07:36 -04:00
Thomas Fleming
f78f2b3b5d Adjust attributes in PMA checker 2021-05-03 21:58:32 -04:00
Thomas Fleming
5c5f181b7a Get MMU tests working in OVPsim 2021-05-03 21:58:05 -04:00
David Harris
96e90402c5 Rolled back fflush on uart. Use -syncio in Modelsim command line instead. 2021-05-03 20:04:44 -04:00
David Harris
81bfc42be5 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-03 19:51:54 -04:00
David Harris
062120f944 Flush uart print statements on \n 2021-05-03 19:51:51 -04:00
Elizabeth Hedenberg
2358db039d coremark update 2021-05-03 19:42:00 -04:00
David Harris
743011194b Flush uart print statements on \n 2021-05-03 19:41:37 -04:00
David Harris
4285d60041 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-03 19:37:56 -04:00
David Harris
8758b6efa1 Flush uart print statements on \n 2021-05-03 19:37:45 -04:00
Elizabeth Hedenberg
08bfaeffe3 coremark print statment 2021-05-03 19:35:08 -04:00
Elizabeth Hedenberg
800f799b7c coremark updates 2021-05-03 19:35:07 -04:00
Elizabeth Hedenberg
d06ad058a4 coremark update 2021-05-03 19:35:07 -04:00
Elizabeth Hedenberg
9e0ce2de61 Coremark objump push 2021-05-03 19:35:07 -04:00
Elizabeth Hedenberg
81ed9b5d06 coremark directory changes 2021-05-03 19:35:06 -04:00
David Harris
2f5649832a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-03 19:29:01 -04:00
David Harris
1f2da4c457 Flush uart print statements on \n 2021-05-03 19:25:28 -04:00
Ross Thompson
6a01ea9f2d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-03 16:57:36 -05:00
Domenico Ottolia
e59f8037be Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-03 17:56:05 -04:00
Ross Thompson
21c0ee0cf2 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-03 16:56:00 -05:00
Ross Thompson
ed4f2ecb24 fixed subtle typo in icache fsm. Was messing up hit spill hit. 
I believe the mibench qsort benchmark runs after this icache fix.
 2021-05-03 16:55:36 -05:00
Domenico Ottolia
ab68933466 Fix bug that caused stvec to get the wrong value 2021-05-03 17:54:57 -04:00
Thomas Fleming
3f7061d557 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-03 17:38:13 -04:00
Thomas Fleming
86a93d77b4 Implement PMP checker and revise PMA checker 2021-05-03 17:37:42 -04:00
Thomas Fleming
00c3b5a033 Remove remnants of InstrReadC 2021-05-03 17:36:25 -04:00
Jarred Allen
a21b84e2ad Add lint to regression 2021-05-03 17:32:05 -04:00
Ross Thompson
0a44d4dd4e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-03 14:53:54 -05:00
Ross Thompson
e09ac73eaf Removed combinational loops between icache and PMA checker. 2021-05-03 14:51:25 -05:00
Ross Thompson
7185905f7b Reduced icache to 1 port memory. 2021-05-03 14:47:49 -05:00
David Harris
699a8f3ac3 Extended maximum signature length to 1M 2021-05-03 15:29:20 -04:00
Katherine Parry
3f05e31954 fpu warnings fixed/commented 2021-05-03 19:17:09 +00:00
Thomas Fleming
94d734cca9 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ebu/ahblite.sv
 2021-05-03 14:02:19 -04:00
Ross Thompson
12b978fec2 Eliminated extra register and fixed ports to icache. 
Still need to support physical tag check and write in icache memory.
Still need to reduce to 1 port SRAM in icache.
I would like to refactor the icache code.
 2021-05-03 12:04:54 -05:00
bbracker
8ec0d18444 merge conflict resolved -- Ross and I made the same fix 2021-05-03 10:10:42 -04:00
bbracker
1db608fbc6 small rv64 plic test bugfix 2021-05-03 10:06:44 -04:00
Ross Thompson
fdf4954a20 Added back in function name to wave.do 2021-05-03 09:04:48 -05:00
Ross Thompson
b57c187208 Fixed typo in ifu for bypassing branch predictor. 
Fixed missing signal name in local history predictor.
 2021-05-03 08:56:45 -05:00
David Harris
c9806fb472 Fixed lint error in div 2021-05-03 09:26:12 -04:00
bbracker
fb0910d9c0 ifu lint fixes 2021-05-03 09:25:22 -04:00