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Author SHA1 Message Date
Harshini Srinath
469b03577d Fixed formatting 2023-07-30 17:39:37 -07:00
Harshini Srinath
141384f60f Fixed formatting 2023-07-30 17:38:22 -07:00
Harshini Srinath
bbbd5f6b2d Fixed spacing 2023-07-30 17:32:46 -07:00
Harshini Srinath
d7b2d84124 Fixed spacing 2023-07-30 17:22:40 -07:00
Harshini Srinath
b129068a92 Fixed spacing 2023-07-30 17:21:52 -07:00
Harshini Srinath
49823ccd45 Fixed spacing 2023-07-30 17:21:22 -07:00
Harshini Srinath
36108e4b52 Fixed spacing 2023-07-30 17:18:25 -07:00
Harshini Srinath
d88b2fd9c1 Fixed spacing 2023-07-30 16:59:27 -07:00
Harshini Srinath
d69d0ececc Fixed spacing 2023-07-30 16:57:57 -07:00
harshinisrinath
b4cfdf3393 Fixed bug and tried to reset menvcfg to improve testing of csri in priv. 2023-07-30 16:40:06 -07:00
David Harris
d58ece3d44 renamed test-shared.vh to config-shared.vh 2023-07-30 05:22:39 -07:00
David Harris
28823aca6e Cleaned up lint for plic_apb part select 2023-07-30 02:00:38 -07:00
David Harris
654cafb7f7 Fixed Questa warnings in plic_apb about part select out of bounds 2023-07-30 01:54:41 -07:00
Jacob Pease
df6db12bbe Merge branch 'main' of github.com:openhwgroup/cvw 2023-07-28 12:49:19 -05:00
David Harris
b47ce62a97 Merge pull request #371 from ross144/main 
Fixed a very subtle combinational loop bug the SSTC implementation of csrs.sv.  STIMCMPH did not assign all XLEN bits of CSRSReadValM so dc_shell produced d-latches and vivado created a combinational loop.
 2023-07-28 09:51:58 -07:00
Ross Thompson
c216f6c014 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-07-28 11:23:17 -05:00
Ross Thompson
7e06775135 Fixed a very subtle combinational loop bug the SSTC implementation of csrs.sv. STIMCMPH did not assign all XLEN bits of CSRSReadValM so dc_shell produced d-latches and vivado created a combinational loop. 2023-07-28 11:20:29 -05:00
Jacob Pease
55055aa0a8 Updated VCU108 device tree for 256MB memory. 2023-07-27 17:44:31 -05:00
Ross Thompson
aa48246778 Merge pull request #370 from JacobPease/main 
Fixed GPIO pin names in fpgaTop.v
 2023-07-27 16:10:44 -04:00
Jacob Pease
9d33e08dbb Removed non-existent SDC dependency from VCU targets in FPGA Makefile. 2023-07-27 15:01:20 -05:00
Jacob Pease
81c6b7e05e Merge branch 'main' of github.com:openhwgroup/cvw 2023-07-27 14:46:01 -05:00
David Harris
8218d806bd Merge pull request #369 from ross144/main 
Fixed issue #368 lint, but not simulation
 2023-07-26 13:32:02 -07:00
Ross Thompson
15dc76310e Fixed lint errors for issue #368. Does not fix simulation errors. We made a design decision a long time ago to not support DTIM on the rv32gc config because LLEN was greater than XLEN. 2023-07-26 15:08:01 -05:00
Jacob Pease
b626f2185a Fixed GPIO pin names in fpgaTop.v 2023-07-25 20:57:04 -05:00
David Harris
1f35023757 Merge pull request #367 from ross144/main 
Complete removal of old flash card hardware and updates to Arty A7 to push clock speed to 20Mhz and increase memory to 256 MiB
 2023-07-25 15:26:08 -07:00
Ross Thompson
2dac02c14c Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-07-25 15:13:07 -05:00
Ross Thompson
dbf9e5da0b Updated Arty A7 fpga config and device tree to 256MiB main memory. 2023-07-25 15:11:47 -05:00
Ross Thompson
e3bcf10185 Merge pull request #366 from davidharrishmc/dev 
Progress toward DC synthesis
 2023-07-25 11:39:49 -04:00
David Harris
ca62487e4c Formatting cleanup 2023-07-25 05:11:38 -07:00
David Harris
46c62aff81 Progress toward synthesis with parameterized design 2023-07-25 05:10:53 -07:00
Ross Thompson
0ae9e8bfde Removed old sdc from all configs. 2023-07-24 15:55:22 -05:00
Ross Thompson
b1f7a5768f Removed all old references to the old flash card controller. 
Added git submodule for the flash card in addins.
Replicated flash card top level for our changes into the fpga/src directory.
 2023-07-24 15:45:57 -05:00
David Harris
208e1e4803 Fixed synthesis Makefile to match new configuration 2023-07-24 11:32:46 -07:00
Ross Thompson
e99c6e5e1d Updated arty a7 device clock speed for 20Mhz. 2023-07-24 11:50:00 -05:00
Ross Thompson
49b87d4550 Merge branch 'main' of github.com:ross144/cvw 2023-07-24 10:47:05 -05:00
Ross Thompson
065e5e98c9 Improved timing constraints for arty a7 to push clock speed to 20Mhz. 2023-07-24 10:46:49 -05:00
harshinisrinath
413a104b6c Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-07-23 11:59:43 -07:00
David Harris
f4c05be987 Merge pull request #364 from ross144/main 
Updated to the newest vivado and required removing the paramized enum. Also includes Jacob's SD card updates and new boot process.
 2023-07-22 18:52:24 -07:00
Ross Thompson
63afd95ad3 Fixed bugs in boot and new flash card merge. Works with arty a7 now. 2023-07-22 15:52:25 -05:00
Ross Thompson
481f27e3fe Updated arty a7 device tree. 2023-07-21 19:08:45 -05:00
Ross Thompson
ab6ef5bb58 At least it simulates and gets through fpga elaboration. 2023-07-21 18:40:26 -05:00
Ross Thompson
a89a1e675c Merge branch 'boot' into mergeBoot 
Merges Jacob's new sdc controller into wally.
 2023-07-21 17:43:45 -05:00
Ross Thompson
f895898d22 Improved the critical path even more. The Arty A7 works upto 19Mhz easily. Testing out 22Mhz now. 2023-07-21 16:31:26 -05:00
Ross Thompson
6a996cd8bf Merge pull request #365 from JacobPease/boot 
Boot
Jacob's account is passing the ECA, but there are some old commits from Jan on James Stine's account which are already in the repo which were merged into this pull request which appear as anonymous users. I don't think it's possible to fix this without a significant headache.  We'd have to cherry-pick each of Jacob's 21 commits.  I'm planning to merge his work into main today/weekend and this will make the job harder. Since these commits are already part of main I'm going to merge this.
 2023-07-21 17:26:41 -04:00
Ross Thompson
d04d2afed2 Modified the LSU/IFU and caches to improve critical path. Arty A7 went from 15 to 17Mhz. I believe we can push all the way to 20+Mhz with relatively little effort. Along the way I'm fixing up the scripts build the linux images for the flash card. 2023-07-21 13:06:27 -05:00
Jacob Pease
380d96b359 Working new boot process. Buildroot package for sdc. 2023-07-20 14:15:59 -05:00
Ross Thompson
2752e5de4c Fixed a bunch of timing constraints for the arty a7 board. 2023-07-19 17:08:16 -05:00
Ross Thompson
c0966c32e5 Improved critical path. 2023-07-19 14:59:37 -05:00
Ross Thompson
538efaf771 Optimized critial path in ifu's spill logic. 2023-07-19 14:13:46 -05:00
Ross Thompson
97a16f75dc Fixed typo in fpga top for arty a7. 2023-07-19 11:37:29 -05:00