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2,185 Commits 4 Branches 2 Tags 52 MiB
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29 Commits

Author SHA1 Message Date
David Harris
f4957fdac1 Renamed dtim->ram and boottim ->bootrom 2021-12-14 13:43:06 -08:00
Kevin
b928d01bb8 dot stars conversions on the rest of the testbenches 2021-12-12 17:53:26 -08:00
Kevin
78fbe542a9 edited one testbench, yet to run regression 2021-12-10 20:26:20 -08:00
Ross Thompson
e1249f4312 Updated coremark testbench with the extra ports from FPGA merge. 
Fixed coremark Makefile to create work directory.
 2021-12-08 13:40:32 -06:00
Ross Thompson
e43aa6ead4 Merge branch 'main' into fpga 2021-11-29 10:06:53 -06:00
David Harris
fb3f267645 Coremark Cleanup, trying compile from addins 2021-11-19 06:09:04 -08:00
David Harris
d243f4bcd1 Cleaning up CoreMark benchmark 2021-11-18 20:12:52 -08:00
David Harris
54fef3e2ca vert "Simplifying riscv-coremark" 
This reverts commit bdc212cf88.
 2021-11-18 18:40:13 -08:00
David Harris
bdc212cf88 Simplifying riscv-coremark 2021-11-18 17:15:40 -08:00
David Harris
b996598b37 CoreMark testing 2021-11-18 16:14:25 -08:00
Ross Thompson
0f87f68b9d Added either the sdModel or constant driver for the SDC ports in all test benches. 2021-09-24 12:31:51 -05:00
Ross Thompson
ef66cdeecf Moved the test bench modules to a common directory. 2021-07-30 14:16:14 -05:00
David Harris
aef408af58 Reversed [0:...] with [...:0] in bus widths across the project 2021-06-21 01:17:08 -04:00
Elizabeth Hedenberg
08bfaeffe3 coremark print statment 2021-05-03 19:35:08 -04:00
Elizabeth Hedenberg
800f799b7c coremark updates 2021-05-03 19:35:07 -04:00
Elizabeth Hedenberg
81ed9b5d06 coremark directory changes 2021-05-03 19:35:06 -04:00
Thomas Fleming
d281ecd067 Remove imem from testbenches 2021-04-14 20:20:34 -04:00
ushakya22
ba01d57767 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-30 15:25:07 -04:00
Teo Ene
1e691e120b Fix typo from last commit 2021-03-24 17:09:58 -05:00
Teo Ene
6a7b69ff2d Updated coremark_bare testbench for IM 2021-03-24 17:04:43 -05:00
Shreya Sanghai
804407eab7 fixed minor bugs in testbench 2021-03-18 17:37:10 -04:00
Teo Ene
0ff785549e Switched coremark to RV64IM 2021-03-17 22:39:56 -05:00
Teo Ene
db164462ed adapted coremark bare testbench to new dtim RAM HDL 2021-03-17 16:59:02 -05:00
Teo Ene
29634f1475 Temporarily reverted my last few commits 2021-03-17 15:16:01 -05:00
Teo Ene
90946d61c5 fix to last commit 2021-03-17 15:02:15 -05:00
Teo Ene
ca901513c8 Added Ross's addr lab stuff to coremark stuff 2021-03-17 14:50:54 -05:00
Elizabeth Hedenberg
bccd37d778 fixing coremark branch prediction 2021-03-17 15:15:55 -04:00
Teo Ene
27a807db95 Added stop to coremark_bare testbench 2021-03-04 07:47:07 -06:00
Teo Ene
2723b21988 Linux CoreMark and baremetal CoreMark split into two separate tests/configs 2021-03-04 07:44:33 -06:00