slmnemo
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0bfc3fda1b
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Fixed UART FIFO bugs and added FIFO tests
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2022-07-22 17:13:19 -07:00 |
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David Harris
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07c946bb04
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Reset MSR on read
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2022-07-22 04:29:27 +00:00 |
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slmnemo
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bfa500234d
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Fixed UART bug related to parity and MSR/LSR
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2022-07-21 20:35:46 -07:00 |
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Katherine Parry
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270216dd02
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radix-4 division integrated into srt - not tested
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2022-07-21 19:38:06 +00:00 |
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Katherine Parry
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67c99d3d1a
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added input enables and improved forwarding
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2022-07-21 01:20:06 +00:00 |
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Katherine Parry
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e8c9830b88
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turn off 2 word store durring non-fp instructions
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2022-07-20 21:57:23 +00:00 |
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Katherine Parry
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fb890d621d
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moved ctrl signal registers into fctrl, also a lot of code cleaning
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2022-07-20 02:27:39 +00:00 |
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cturek
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db39a05abc
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small changes
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2022-07-20 01:36:25 +00:00 |
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Katherine Parry
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afcddf7035
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oprimized zeros and replaced complex ?: with always_comb
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2022-07-19 23:44:37 +00:00 |
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Katherine Parry
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4c2afbbc4f
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moved Se into execute stage
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2022-07-19 01:10:10 +00:00 |
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Katherine Parry
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a590728350
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reworked fmashiftcalc to match book
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2022-07-19 00:04:24 +00:00 |
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David Harris
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59eb11b73a
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-18 23:11:12 +00:00 |
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Katherine Parry
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e599f82b29
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moved Ss to execute stage
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2022-07-18 20:48:56 +00:00 |
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Katherine Parry
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921debf930
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removed underflow from inexactct calculation
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2022-07-18 17:51:18 +00:00 |
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Katherine Parry
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ea7b32a50b
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-18 17:31:29 +00:00 |
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Katherine Parry
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5bb1478859
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renamed signals in ocde to match book
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2022-07-18 17:31:17 +00:00 |
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David Harris
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7c744f0053
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Rewrote convert shift calculation with always for ease of reading
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2022-07-17 16:40:58 +00:00 |
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David Harris
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6e1d4ec4ed
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restored intPending logic to be sticky for PLIC
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2022-07-16 17:43:31 -07:00 |
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Katherine Parry
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a4cd157f00
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forgot some files
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2022-07-15 21:42:45 +00:00 |
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Katherine Parry
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e251022269
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merged floating-point radix-2 divider with radix-4
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2022-07-15 20:16:59 +00:00 |
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Katherine Parry
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b069cfbec2
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fixed error in divsqrt
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2022-07-14 18:16:00 +00:00 |
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Katherine Parry
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e5a8ac2a44
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renamed a file to fit diagram
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2022-07-13 23:44:54 +00:00 |
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Katherine Parry
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7e163e22a3
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some code cleanup
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2022-07-13 15:28:22 -07:00 |
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Katherine Parry
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77ea4e47cb
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removed minus 1 case in rounding
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2022-07-13 15:01:38 -07:00 |
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Katherine Parry
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26e39dd325
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removed the +1 in the cvt
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2022-07-13 09:41:35 -07:00 |
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Katherine Parry
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e05b2a07d2
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removed warnings and took a mux out of the critical path
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2022-07-12 18:32:17 -07:00 |
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Katherine Parry
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452b017f9a
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found the bug in the store modification
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2022-07-12 22:42:19 +00:00 |
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Katherine Parry
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2ada8a8bc1
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-12 22:37:20 +00:00 |
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Katherine Parry
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5c0ecfa433
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forgot a file
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2022-07-11 18:31:51 -07:00 |
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Katherine Parry
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7815b81716
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-11 18:30:29 -07:00 |
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Katherine Parry
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b728e5054d
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variable interations implemented in radix-4 divider
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2022-07-11 18:30:21 -07:00 |
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David Harris
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2bc8ff555b
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added comment about checking SRAM size
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2022-07-10 12:48:51 +00:00 |
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David Harris
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9cb675b2e4
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added comment about RAMs in cacheway
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2022-07-10 12:47:34 +00:00 |
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Katherine Parry
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ca4fe08fd9
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renamed FLoad2 to FStore2
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2022-07-09 00:26:45 +00:00 |
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Katherine Parry
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cd53ae67d9
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moved fpu ieu write data mux to lsu
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2022-07-08 23:56:57 +00:00 |
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Katherine Parry
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3476579e02
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-08 12:30:50 -07:00 |
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Katherine Parry
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9ef45f36fd
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renamed signals in cvt and prostproc
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2022-07-08 12:30:43 -07:00 |
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James Stine
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c5dfefe669
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Update SRAM to /proj/wally
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2022-07-08 08:09:55 -05:00 |
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David Harris
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c72e4d43d2
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erge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-08 09:09:07 +00:00 |
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David Harris
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381f3298d8
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Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc
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2022-07-08 09:09:02 +00:00 |
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David Harris
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1ce0975366
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Adjusting byte writes to RAM
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2022-07-08 08:45:21 +00:00 |
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David Harris
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3f9e662201
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Removed subwordwrite mention in cache because sww is needed to replicate data across byte enables
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2022-07-08 08:44:37 +00:00 |
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David Harris
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9b6d9666c5
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Removed unused swbytemask from CLINT
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2022-07-08 08:43:24 +00:00 |
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Katherine Parry
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905b7ffc84
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moved unsused division code again
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2022-07-07 16:41:26 -07:00 |
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Katherine Parry
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2bbde827e6
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Revert "moved old divsqrt to unusedsrc"
This reverts commit c9f5ae12ea .
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2022-07-07 16:29:17 -07:00 |
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Katherine Parry
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c9f5ae12ea
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moved old divsqrt to unusedsrc
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2022-07-07 16:09:56 -07:00 |
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Katherine Parry
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41c16be012
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srt divider merged into fpu
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2022-07-07 16:01:33 -07:00 |
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David Harris
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96a75d7749
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-07 22:00:59 +00:00 |
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Katherine Parry
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08769e35ae
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modified wally shared
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2022-07-07 21:59:43 +00:00 |
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David Harris
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2f342c430e
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fixing port errors
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2022-07-07 21:57:10 +00:00 |
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