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Author SHA1 Message Date
Kip Macsai-Goren
06db4c08ef removed execution tests until fences are implemented 2021-07-16 17:45:54 -04:00
Kip Macsai-Goren
e62b22a72d added backup output files for when execution tests are possible 2021-07-16 17:25:40 -04:00
Kip Macsai-Goren
b7b7c170ec removed execution tests until fences are implemented 2021-07-16 17:24:59 -04:00
Ross Thompson
8d4432e9a7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-16 15:59:13 -05:00
Kip Macsai-Goren
e4f6063b6f More fixes to bring physical address into dtim range 2021-07-16 16:58:28 -04:00
Ross Thompson
e9649eb1f5 Made furture progress in the mmu tests. 2021-07-16 15:56:06 -05:00
Kip Macsai-Goren
7e2d150a57 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-16 16:05:50 -04:00
Ross Thompson
0c9dad2db6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-16 15:04:38 -05:00
Ross Thompson
965f34d78f Added guide for Ben to do linux conversion. 2021-07-16 15:04:30 -05:00
Kip Macsai-Goren
6aeb6c2123 removed exectution tests that intentionally fail as well until fences are implemented. 2021-07-16 15:47:08 -04:00
Kip Macsai-Goren
81ea24d25b removed execution tests that are supposed to pass until fences are implemented. 2021-07-16 15:32:13 -04:00
Ross Thompson
abce241f68 Also changed the shadow ram's dcache copy widths. 
Merge branch 'dcache' into main
 2021-07-16 14:21:09 -05:00
Ross Thompson
6ab7cd0f4d Updated the config so the tim has a bigger range. 2021-07-16 12:35:00 -05:00
Ross Thompson
bebc7cc5e3 Updated wave file. 2021-07-16 12:34:37 -05:00
Ross Thompson
d3715acf2d Fixed walker fault interaction with dcache. 2021-07-16 12:22:13 -05:00
bbracker
e51ab63a86 reduce number of UART ports to 1 2021-07-16 12:42:29 -04:00
bbracker
c7712d035b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-16 12:27:25 -04:00
bbracker
d38109bc1c changed stop of linux boot from arch_cpu_idle to do_idle 2021-07-16 12:27:15 -04:00
Ross Thompson
5ca7dc619c Updated the ptw, lsuarb and dcache to hopefully solve the interlock issues. 2021-07-16 11:12:57 -05:00
bbracker
f7092c60d1 incremental linux config de-bloating 2021-07-16 12:08:58 -04:00
bbracker
629d48f20f incremental linux config de-bloating 2021-07-16 11:33:11 -04:00
bbracker
0f1060ceb7 incremental linux config de-bloating 2021-07-16 11:15:25 -04:00
bbracker
fcb63a409a incremental linux config de-bloating 2021-07-16 01:58:21 -04:00
bbracker
0a1aa821b8 incremental linux config de-bloating 2021-07-16 01:54:36 -04:00
bbracker
149be959e0 incremental linux config de-bloating 2021-07-16 01:43:16 -04:00
bbracker
e5e3a60574 incremental linux config de-bloating 2021-07-16 01:33:51 -04:00
bbracker
7266b29656 incremental linux config de-bloating 2021-07-16 01:25:41 -04:00
bbracker
09de4ded87 incremental linux config de-bloating 2021-07-16 01:00:12 -04:00
bbracker
f7b43211ac incremental linux config de-bloating 2021-07-16 00:46:22 -04:00
bbracker
c5e9734851 incremental linux config de-bloating 2021-07-16 00:41:18 -04:00
bbracker
d6a4b8ccfa incremental linux config de-bloating 2021-07-16 00:34:41 -04:00
bbracker
285e5941e2 incremental linux config de-bloating 2021-07-16 00:16:12 -04:00
bbracker
a6071f3fb0 incremental linux config de-bloating 2021-07-16 00:10:31 -04:00
bbracker
226474051d incremental linux config de-bloating 2021-07-15 23:53:15 -04:00
bbracker
0a15468fd5 incremental linux config de-bloating 2021-07-15 23:30:24 -04:00
bbracker
588a7d0341 incremental linux config de-bloating 2021-07-15 23:12:21 -04:00
bbracker
703b72fb89 incremental linux config de-bloating 2021-07-15 23:00:20 -04:00
bbracker
847edccbd7 incremental linux config de-bloating 2021-07-15 21:33:52 -04:00
bbracker
2091a7104e incremental linux config de-bloating 2021-07-15 20:54:36 -04:00
Kip Macsai-Goren
f01be12162 fixed output file to match sv48 test again 2021-07-15 18:55:00 -04:00
bbracker
a4f9d7a6e5 working linux config 2021-07-15 18:49:54 -04:00
Kip Macsai-Goren
cc8a28e884 fixed another address to be in tim range 2021-07-15 18:31:53 -04:00
Kip Macsai-Goren
ba5bb12e26 Still broken, midway through fixing understanding of how ptw and datacache interact in time especially wrt adrE, adrM, faults, and tlb interaction. 2021-07-15 18:30:29 -04:00
bbracker
58cbce940a stripped down busybox a bit 2021-07-15 16:07:56 -04:00
Kip Macsai-Goren
53072d55f3 modified sv48 test to only read or write from physical addresses located in the dtim range from 0x80000000 to 0x87FFFFFF 2021-07-15 14:01:29 -04:00
Ross Thompson
96aa106852 Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault. 2021-07-15 11:56:35 -05:00
Ross Thompson
4549a9f1c9 Merge branch 'main' into dcache 2021-07-15 11:55:20 -05:00
Ross Thompson
5fb5ac3d5a Updated wave file. 2021-07-15 11:04:49 -05:00
Ross Thompson
c39a228266 Fixed how the dcache and page table walker stall cpu so that once a tlb miss occurs the CPU is always stalled until the walk is complete, the tlb updated, and the dcache fetched and hits. 2021-07-15 11:00:42 -05:00
Ross Thompson
c954fb510b Renamed DCacheStall to LSUStall in hart and hazard. 
Added missing logic in lsu.
 2021-07-15 10:16:16 -05:00