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Configurable RISC-V Processor
1,353 Commits 4 Branches 2 Tags 53 MiB
SystemVerilog 33.7%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
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Ross Thompson abce241f68 Also changed the shadow ram's dcache copy widths. 
Merge branch 'dcache' into main
2021-07-16 14:21:09 -05:00
riscv-coremark Commented out remaining ehitoa function declaration/calls and related char buff instances. Also commented out extra libraries not currently in use 2021-07-14 04:46:11 -04:00
testsBP Added special tests for checking the accuracy of global and gshare branch 2021-06-04 11:01:54 -05:00
wally-pipelined Also changed the shadow ram's dcache copy widths. 2021-07-16 14:21:09 -05:00
.gitattributes moved shared constants to a shared directory 2021-06-03 22:41:30 -04:00
.gitignore testvector unlinker for dev purposes 2021-07-14 11:05:34 -04:00
.gitmodules Flow updated for 90nm 2021-07-01 13:32:42 -05:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor