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09dc3e1143
Commit Graph

173 Commits

Author SHA1 Message Date
Ross Thompson
09dc3e1143 Merge branch 'main' into fpga 2021-10-20 16:24:55 -05:00
Shreya Sanghai
d783acbbc5 added DESIGN_COMPLIER to forgotten config files 2021-10-12 10:14:04 -07:00
Ross Thompson
5fdac9fa3b Merge branch 'main' into fpga 2021-10-11 18:17:58 -05:00
Shreya Sanghai
51185478df made redunantmul generate DW02_multp for synopsys sythnesis 2021-10-11 11:54:39 -07:00
Ross Thompson
2e0dcaaff9 Fpga simualtion files. 2021-10-11 10:24:40 -05:00
Ross Thompson
3d9d4cc03f Partially working sd card reader. 2021-10-11 10:23:45 -05:00
David Harris
a077735ecc Major reorganization of regression and simulation and testbenches 2021-10-10 15:07:51 -07:00
David Harris
bf0061be66 Reduced cycle count for DIVW/DIVUW by two 2021-10-03 09:42:22 -04:00
David Harris
30ec68d567 Parameterized number of bits per cycle for integer division 2021-10-03 01:10:15 -04:00
Ross Thompson
99070127d8 Added debugging directives to system verilog. 2021-09-27 13:57:46 -05:00
Ross Thompson
232d4a554f Have program which checks for sdc init and issues read, but read done is 
not correctly being read back by the software.  The error is in how the
sdc indicates busy.
 2021-09-24 15:53:38 -05:00
Ross Thompson
af28cfb70c Added SDC defines to each config mode. 
Added sd_top which is the sd card reader.
 2021-09-24 12:24:30 -05:00
Ross Thompson
4256ef82b1 SDC to ABHLite interface partially done. 
Added SDC to adrdec and uncore.
 2021-09-24 10:45:09 -05:00
David Harris
72c1cc33f5 Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression. 2021-09-15 13:14:00 -04:00
Ross Thompson
3b12235954 Fixed FPGA synthesis bug in the fpdiv fsm. Was creating latches. 2021-09-11 15:40:27 -05:00
Ross Thompson
8141a515bb Changed configs to support 4 ways set associative caches. 2021-09-08 12:52:49 -05:00
Ross Thompson
6606eea27e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-09-08 12:47:03 -05:00
Ross Thompson
150a73d6cf Set associate icache working, but way 0 is never written. 2021-09-07 12:46:16 -05:00
Katherine Parry
7607adc951 FMA cleanup 2021-08-28 10:53:35 -04:00
Katherine Parry
567260751a move some FPU select muxs to execute stage 2021-08-13 14:41:22 -04:00
Katherine Parry
21555c392f LZA added to FMA and attemting a merged FMA and adder in synthesis 2021-08-10 13:57:16 -04:00
Ross Thompson
d430659983 fixed the read timer issue but we still have problems with interrupts and i/o devices. 2021-08-06 10:16:06 -05:00
Katherine Parry
67ab0b165c fpu cleanup 2021-07-24 14:59:57 -04:00
bbracker
9dcd5d3622 fix UART RX FIFO bug where tail pointer can overtake head pointer 2021-07-22 02:09:41 -04:00
Katherine Parry
61f81bb76e FMA parameterized 2021-07-20 22:04:21 -04:00
David Harris
20744883df flag for optional boottim 2021-07-20 14:46:37 -04:00
David Harris
c117356432 Parameterized I$/D$ configurations and added sanity check assertions in testbench 2021-07-20 08:57:13 -04:00
Ross Thompson
07c47f0034 Restored TIM range. 2021-07-19 21:17:31 -05:00
David Harris
b2f7952b3d Added cache configuration to config files 2021-07-19 18:19:46 -04:00
David Harris
4729a72167 Updated FMA1 with parameterized size 2021-07-18 20:40:49 -04:00
David Harris
f22b6e7397 Added FLEN, NE, NF to config and started using these in FMA1 2021-07-18 17:28:25 -04:00
David Harris
c29a2ff8df Started atomics 2021-07-17 21:11:41 -04:00
David Harris
f69393f197 Reduced size of physical memory by 16 for performance 2021-07-16 20:10:12 -04:00
Ross Thompson
abce241f68 Also changed the shadow ram's dcache copy widths. 
Merge branch 'dcache' into main
 2021-07-16 14:21:09 -05:00
Ross Thompson
6ab7cd0f4d Updated the config so the tim has a bigger range. 2021-07-16 12:35:00 -05:00
Katherine Parry
701ea38964 Fixed lint warning 2021-07-14 21:24:48 -04:00
Katherine Parry
acdd2e4504 Fixed writting MStatus FS bits 2021-07-13 13:20:30 -04:00
Katherine Parry
0cc07fda1b Almost all convert instructions pass Imperas tests 2021-07-11 18:06:33 -04:00
Abe
09a092abd5 Updated MISA defining as well as porting sizes for peripherals (34 to 56) 2021-07-07 02:37:09 -04:00
David Harris
a390736f26 Don't generate HPTW when MEM_VIRTMEM=0 2021-07-05 23:35:44 -04:00
David Harris
8ca7abaa02 Added support for TVM flag in CSRS and to disabl TLB when MEM_VIRTMEM = 0 2021-07-05 20:35:31 -04:00
David Harris
6b9cfe90d8 Added ASID & Global PTE handling to TLB CAM 2021-07-04 17:52:00 -04:00
David Harris
9276446797 Switched to array notation for pmpchecker 2021-07-04 10:51:56 -04:00
David Harris
c897bef8cd Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang. 2021-07-04 01:19:38 -04:00
Ross Thompson
46831035fb Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-02 13:56:49 -05:00
Ross Thompson
549b7b2a62 Merge branch 'main' into bigbadbranch 2021-07-02 11:52:26 -05:00
David Harris
cd6cabac2f Optimized PMP checker logic and added support for configurable number of PMP registers 2021-07-02 11:05:25 -04:00
Ross Thompson
17636b3293 Regression test runs further. The LSU state machine which fakes the Dcache had a few bugs. MemAccessM needed to be squashed on bus faults. 2021-06-25 11:05:17 -05:00
Kip Macsai-Goren
1485d29dde Light cleanup of signals, style. Changed several signals to account for new Phys Addr sizes as opposed to HADDR. 2021-06-24 20:01:11 -04:00
Ross Thompson
0377d3b2c9 Progress. 2021-06-24 13:05:22 -05:00