Ross Thompson
b6e5670bc3
Added CommitedM to data cache output.
2021-07-13 22:43:42 -05:00
bbracker
eb8c1bf5e7
needed to create a directory for gdb script
2021-07-13 19:39:57 -04:00
Ross Thompson
278bbfbe3c
Partially working changes to support uncached memory access. Not sure what CommitedM is.
2021-07-13 17:24:59 -05:00
Abe
8d445ef508
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-13 18:22:36 -04:00
Kip Macsai-Goren
f0bf48bbfb
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-13 17:41:47 -04:00
James E. Stine
45a6e96673
mod 2 of fpdivsqrt update
2021-07-13 16:59:17 -04:00
James E. Stine
d695be3ad0
Update fpdivsqrt item until move into uarch
2021-07-13 16:53:20 -04:00
bbracker
2036be2ea4
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-13 16:16:04 -04:00
bbracker
dff3970d1c
changed QEMU to use different ports
2021-07-13 16:15:51 -04:00
Ross Thompson
b780e471b4
Fixed interaction between icache stall and dcache. On hit dcache needs to enter a cpu busy state when the cpu is stalled.
2021-07-13 14:51:42 -05:00
Ross Thompson
51249a0e04
Fixed the fetch buffer accidental overwrite on eviction.
2021-07-13 14:21:29 -05:00
Ross Thompson
2034a6584f
Dcache AHB address generation was wrong. Needed to zero the offset.
2021-07-13 14:19:04 -05:00
Ross Thompson
ee09fa5f58
Moved StoreStall into the hazard unit instead of in the d cache.
2021-07-13 13:20:50 -05:00
David Harris
516b710db6
Fixed busybear by restoring InstrValidW needed by testbench
2021-07-13 14:17:36 -04:00
Ross Thompson
2004b2e044
Fixed back to back store issue.
...
Note there is a bug in the lsuarb which needs to arbitrate a few execution stage signals.
2021-07-13 12:46:20 -05:00
Abe
d71b99383f
Downloaded clean version of Coremark from EEMBC github page with which to benchmark RISCV-Wally
2021-07-13 13:37:40 -04:00
David Harris
9af5cef65a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-13 13:26:51 -04:00
David Harris
283c2cda0e
added or.sv
2021-07-13 13:26:40 -04:00
Katherine Parry
b9edbb15eb
Fixed writting MStatus FS bits
2021-07-13 13:22:04 -04:00
Katherine Parry
acdd2e4504
Fixed writting MStatus FS bits
2021-07-13 13:20:30 -04:00
David Harris
3427d2b7d6
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-13 13:19:24 -04:00
David Harris
68d1f87101
Fixed InstrValid from W to M stage for CSR performance counters
2021-07-13 13:19:13 -04:00
bbracker
90eb84cc61
updated buildroot make procedure to incorporate configs more robustly
2021-07-13 12:40:14 -04:00
Ross Thompson
40922cf064
Fixed subword write. subword read should not feed into subword write.
2021-07-13 11:21:44 -05:00
Ross Thompson
a314b3cf68
restored rv64ic config back to full sized dtim.
2021-07-13 11:18:54 -05:00
Ross Thompson
d3ffbe0e5d
Modularized the shadow memory to reduce performance hit.
2021-07-13 10:55:57 -05:00
Ross Thompson
17dc488010
Got the shadow ram cache flush working.
2021-07-13 10:03:47 -05:00
bbracker
471fe8ab31
whoops I accidentally made main.config into a symbolic link; now it is a source file
2021-07-13 11:00:01 -04:00
bbracker
be81912c52
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-13 10:04:13 -04:00
bbracker
497d8e3f16
working config for a buildroot that boots
2021-07-13 10:04:09 -04:00
David Harris
4be1e8617f
Replaced .or with or_rows structural code in MMU read circuitry for synthesis.
2021-07-13 09:32:02 -04:00
Ross Thompson
9fe6190763
Team work on solving the dcache data inconsistency problem.
2021-07-12 23:46:32 -05:00
Ross Thompson
6b42b93886
Now updates the dtim with the dirty data in the dcache.
...
Simulation is showing issues. It lookslike the cache is not
evicting the correct data.
2021-07-12 15:13:27 -05:00
Ross Thompson
8ca8b9075d
Progress towards the test bench flush.
2021-07-12 14:22:13 -05:00
Katherine Parry
a4bd128978
fcvt.sv cleanup
2021-07-11 21:30:01 -04:00
Katherine Parry
0cc07fda1b
Almost all convert instructions pass Imperas tests
2021-07-11 18:06:33 -04:00
bbracker
05f9fa65bf
rootfs.cpio no longer overlaps
2021-07-11 05:11:12 -04:00
Ross Thompson
282bde7205
Fixed the spurious AHB requests to address 0. Somehow by not having a default
...
(else) in the fsm branch selection for STATE_READY in the d cache it was
possible to take an invalid branch through the fsm.
2021-07-10 22:34:47 -05:00
Ross Thompson
d9fa3af94d
Loads are working.
...
There is a bug when the icache stalls 1 cycle before the d cache.
2021-07-10 22:15:44 -05:00
Ross Thompson
a82c4c99c2
Actually writes the correct data now on stores.
2021-07-10 17:48:47 -05:00
Ross Thompson
ee72178eec
Write miss with eviction works.
2021-07-10 15:17:40 -05:00
Ross Thompson
0a6c86af94
Write Hits and Write Misses without eviction are working correctly! The next
...
step is to add eviction of dirty lines.
2021-07-10 10:56:25 -05:00
bbracker
e77a9169b6
greatly stripped down unused stuff in linux config
2021-07-10 11:53:35 -04:00
David Harris
488cfa16ff
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-09 19:18:35 -04:00
David Harris
e6fb590187
added missing tlbmixer.sv
2021-07-09 19:18:23 -04:00
bbracker
4556098f0a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-09 18:56:28 -04:00
bbracker
e4f62e32ba
fix_mem.py bugfix
2021-07-09 18:56:17 -04:00
Ross Thompson
94b29ec418
Loads in modelsim, but the first store double does not function correctly. The write address is wrong so the cache is updated using the wrong address.
...
I think this is do to the cycle latency of stores. We probably need extra muxes to select between MemPAdrM and MemPAdrW depending on if the write is a
full cache block or a word write from the CPU.
2021-07-09 17:14:54 -05:00
bbracker
b2cb86d55c
organize/update buildroot scripts for new image
2021-07-09 17:03:47 -04:00
Ross Thompson
7e98610651
Design loads in modelsim, but trap is an X.
2021-07-09 15:37:16 -05:00
