David Harris
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aef408af58
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Reversed [0:...] with [...:0] in bus widths across the project
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2021-06-21 01:17:08 -04:00 |
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Katherine Parry
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e4db6ea6f5
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fixed lint warnings for fpu and lzd
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2021-06-05 12:06:33 -04:00 |
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Ross Thompson
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db2a38c300
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Fixed a few lint errors,
clock gater was wrong,
missing signal definitions in branch predictor.
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2021-06-02 09:33:24 -05:00 |
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Ross Thompson
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7afbd8d877
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The clock gater was not implemented correctly. Now it is level sensitive to a low clock.
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2021-06-01 15:05:22 -05:00 |
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Ross Thompson
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8e330367ac
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added clock gater to floating point divider to speed up simulation time.
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2021-06-01 13:46:21 -05:00 |
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James E. Stine
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889b935630
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Modify elements of generics for LZD and shifter wrote for integer
divider.
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2021-05-31 08:36:19 -04:00 |
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Noah Boorstin
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2d1f63b590
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change flop in ahb controller to use normal flop module
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2021-03-10 19:14:02 +00:00 |
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David Harris
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6f4e8b723e
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Initial (untested) implementation of lr and sc
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2021-03-01 00:09:45 -05:00 |
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David Harris
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cd4ba8831c
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Merged bus into main
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2021-02-25 00:28:41 -05:00 |
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David Harris
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adc5d5bc1a
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Added MUL
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2021-02-15 22:27:35 -05:00 |
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David Harris
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cc42655789
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More memory interface, ALU testgen
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2021-02-15 10:10:50 -05:00 |
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David Harris
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07af481b67
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Reorganized src hierarchically
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2021-01-30 11:50:37 -05:00 |
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