264 Commits

Author	SHA1	Message	Date
Rose Thompson	02ab9fe99c	Fixed all the bugs associated with the signature and the store side of misaligned access. Load misaligned is still causing some issues.	2023-11-10 17:58:42 -06:00
Rose Thompson	bd866e1025	Fixed some more bugs in the Zicclsm signature.	2023-11-10 17:36:10 -06:00
Rose Thompson	efecb0c346	Fixed bug in the Zicclsm test.	2023-11-10 17:34:23 -06:00
Rose Thompson	ada354f443	Fixed bug in the misaligned access test.	2023-11-10 17:02:15 -06:00
Rose Thompson	b74bfbeefd	Merge branch 'main' into Zicclsm	2023-11-10 16:15:32 -06:00
naichewa	d67badfc60	fix hardware interlock, hold mode deassert	2023-11-08 15:20:51 -08:00
naichewa	a5837eb62c	fifo fixes and edge case testing	2023-11-07 17:59:46 -08:00
naichewa	4651b807ed	added test cases	2023-11-02 15:43:08 -07:00
Rose Thompson	0a4ed5515b	Merge branch 'main' into Zicclsm	2023-11-02 12:55:51 -05:00
Rose Thompson	afa1d85e3b	Doesn't yet fully work. ... Thomas is going to finish debugging while I'm on the RISCV summit next week.	2023-11-02 12:07:42 -05:00
Rose Thompson	7ba891f607	Progress. I think the remaining bugs are in the regression test's signature.	2023-11-01 17:51:48 -05:00
naichewa	9aa8a7af3e	comments, more test cases	2023-11-01 01:26:34 -07:00
Rose Thompson	5660eff57d	Working through issues with the psill logic.	2023-10-31 18:50:13 -05:00
Rose Thompson	4984b3935f	Progress	2023-10-31 14:50:33 -05:00
Rose Thompson	5ca428d6a8	Fixed bugs in misaligned test.	2023-10-31 12:49:35 -05:00
Rose Thompson	c061440141	First stab at the misaligned test.	2023-10-31 12:30:10 -05:00
naichewa	7dd3f24d6c	Merge branch 'main' into spi	2023-10-30 17:01:41 -07:00
naichewa	2330f4ee63	hardware interlock	2023-10-30 17:00:20 -07:00
Rose Thompson	2241976d29	Updated mmu to not generate trap on cacheable misaligned access when supported. ... Updated tests with David's help.	2023-10-30 18:26:11 -05:00
David Harris	f6a7f707bd	Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder.	2023-10-30 09:56:17 -07:00
Rose Thompson	0fd5b3b2ce	Updated comments in the cboz tests.	2023-10-20 15:15:47 -05:00
Rose Thompson	5a4028064a	Updated comments for the cbom tests.	2023-10-20 15:13:52 -05:00
naichewa	0ff9ce527d	Merge branch 'main' into spi	2023-10-16 22:59:50 -07:00
David Harris	ac4216b43d	Incorporated new AMO tests from riscv-arch-test	2023-10-16 10:25:45 -07:00
David Harris	6245748ed7	Added CSR permission tests for mconfigptr, menvcfg, mseccfg, etc.	2023-10-15 15:31:03 -07:00
David Harris	b4891d88db	Added WALLY minfo test for rv32	2023-10-15 06:48:22 -07:00
David Harris	434d6b2c5c	minfo test working again with mconfigptr for RV64	2023-10-15 06:41:52 -07:00
naichewa	aa5abfc8e8	always working after reg bit swizzle changes	2023-10-13 14:22:32 -07:00
naichewa	f231c3d3a3	correct delay0, fmt register test entries	2023-10-12 15:13:23 -07:00
naichewa	d5d4f9d044	transferred spi changes in ECA-authorized commit	2023-10-12 13:36:57 -07:00
David Harris	d526d28804	Added MENVCFG.HADE bit and updated SVADU to depend on this bit	2023-10-04 09:34:28 -07:00
Ross Thompson	12c3c98824	Extended the CBOM test to cover a 4 way set associative cache with 4KiB ways.	2023-08-30 11:29:44 -05:00
David Harris	8d3ff59673	Completed basic tests of svnapot and svpbmt	2023-08-28 06:57:35 -07:00
Ross Thompson	cd3349bd26	Added rv32 cboz test.	2023-08-24 17:02:53 -05:00
Ross Thompson	914b6f9734	Now have CBOZ instructions working!	2023-08-24 16:47:35 -05:00
Ross Thompson	7d51690b7c	Oups forgot to include the 32-bit cbom test in previous commit.	2023-08-24 09:04:41 -05:00
Ross Thompson	310b700550	Have a working 32 bit cbom test!	2023-08-21 13:46:09 -05:00
Ross Thompson	d4c6ba627d	Working CBO tests for 64 bit!	2023-08-21 12:55:07 -05:00
Ross Thompson	5ed096e4bc	Made a bunch of progress towards getting cbo instructions tested.	2023-08-21 11:46:21 -05:00
David Harris	c137a1c8cf	Fixed timer interrupt testing	2023-06-09 17:20:41 -07:00
David Harris	f68b9c224a	Fixed WALLY-trap test case to use menvcfg	2023-06-09 15:24:26 -07:00
David Harris	b70b0c7c5e	Added support for menvcfg and senvcfg, including menvcfg.STCE for supervisor timer compare	2023-06-09 14:40:01 -07:00
David Harris	19096a812a	Added Zifencei ISA to tests where necessary to support new compiler	2023-05-16 11:18:27 -07:00
David Harris	0a7a159d69	Added Zicsr and zifencei to RVTEST_ISA in custom tests where necessary to make them compile	2023-05-14 06:58:29 -07:00
Kip Macsai-Goren	34200e8c76	restored original virt mem tests when svadu is not supported	2023-04-11 18:47:08 -07:00
Kip Macsai-Goren	c4766c8a02	renamed virt mem tests to include svadu	2023-04-11 18:46:37 -07:00
Kip Macsai-Goren	b2d6084eea	removed unnecessary 'deadbeef's at the end of reference outputs	2023-04-11 18:32:04 -07:00
Kip Macsai-Goren	a82c0a7780	Modified virt mem tests to do correct r/w when svadu is enabled	2023-04-11 18:08:30 -07:00
Kip Macsai-Goren	e0b938b409	Removed Trap outputs from writes covered by SVADU	2023-04-11 17:41:57 -07:00
Kip Macsai-Goren	a899606c2b	Removed Sail from virt mem tests due to sail not recognizing SVADU	2023-04-11 17:41:31 -07:00