Jordan Carlin
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e6b3257862
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Build nproc linux
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2024-07-24 20:19:30 -07:00 |
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Jordan Carlin
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85b98af958
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Build testvectors with buildroot
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2024-07-24 20:19:30 -07:00 |
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Jordan Carlin
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bbf90b1f4b
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Add cpio to installation for buildroot
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2024-07-24 19:55:18 -07:00 |
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David Harris
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2c7bc7038e
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Merge pull request #892 from ross144/main
Adds synthesizable RVVI FPGA hardware
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2024-07-24 12:21:36 -07:00 |
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Rose Thompson
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ce61429bdf
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Fixed the reset bug in wallyTracer.
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2024-07-24 13:32:46 -05:00 |
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Rose Thompson
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5cae55561e
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Removed unused file.
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2024-07-24 13:30:25 -05:00 |
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Rose Thompson
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df88939bcb
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2024-07-24 13:14:25 -05:00 |
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Rose Thompson
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d0a5b278b7
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Factored out the rvvi testbench code into rvvitbwrapper.
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2024-07-24 13:10:57 -05:00 |
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Rose Thompson
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b1a711ae0f
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Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim.
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2024-07-24 12:47:50 -05:00 |
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Rose Thompson
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27f89fcdbd
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Updated verilog-ethernet to remove all verilator warnings or at least suppress them.
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2024-07-24 10:13:03 -05:00 |
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Jordan Carlin
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bb5c9f9ead
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Switch to logger function and fix exit codes
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2024-07-23 23:42:03 -07:00 |
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Jordan Carlin
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d08deddcc4
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Update logging grep
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2024-07-23 23:40:42 -07:00 |
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Jordan Carlin
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121ee51503
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Fix logging
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2024-07-23 23:40:03 -07:00 |
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Jordan Carlin
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47452ddaaa
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Remove hardcoded /opt/riscv
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2024-07-23 23:29:45 -07:00 |
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Rose Thompson
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9404a339ee
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Handled all remaining verilator warnings in the rvvi synth code. Now it's time to take on the verilog-ethernet warnings.
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2024-07-23 17:44:37 -05:00 |
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Rose Thompson
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6c212ebf0e
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Changes are confirmed to work on the FPGA.
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2024-07-23 17:39:38 -05:00 |
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Jacob Pease
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f1cc7dd5a3
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Fixed verilog bugs.
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2024-07-23 17:26:39 -05:00 |
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Jacob Pease
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dcb2edf888
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Fixed syntax bugs. inline functions are now static and in the spi.h header.
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2024-07-23 17:00:32 -05:00 |
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Rose Thompson
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e8e71ad643
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Code cleanup.
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2024-07-23 16:35:05 -05:00 |
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Jacob Pease
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5f0addd69a
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Initial pass on SPI based bootloader code finished.
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2024-07-23 16:33:49 -05:00 |
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Jacob Pease
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a8b9e7776b
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Added some minor error checking to gpt.c.
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2024-07-23 16:32:52 -05:00 |
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Jacob Pease
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ab00ea5a5c
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Added sd_read64 to help with block reads and crc checking.
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2024-07-23 16:32:29 -05:00 |
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Rose Thompson
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57ea39d685
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Fixed rvvi csr counting.
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2024-07-23 16:22:23 -05:00 |
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Rose Thompson
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54e0289608
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Fixed bugs in the rvvi synth logic which encoded csr instructions.
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2024-07-23 16:16:11 -05:00 |
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Jacob Pease
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57eeba5c8c
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Progress made on implementing new disk read function.
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2024-07-23 15:47:23 -05:00 |
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Jacob Pease
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9ccb0eb027
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Removed references to card_type.
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2024-07-23 15:46:18 -05:00 |
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Jacob Pease
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d9afaade03
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Merge branch 'main' of github.com:openhwgroup/cvw into spiboot
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2024-07-23 14:18:50 -05:00 |
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Jacob Pease
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bf65cd2817
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Added uart print functions and the Wally banner. SD card can now be initialized. Removed old code from boot.c
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2024-07-23 14:18:42 -05:00 |
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Rose Thompson
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1eff86b7ae
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Down to 3 verilator warnings in rvvisynth and a 40 warnings in verilog-ethernet.
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2024-07-23 13:18:03 -05:00 |
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Rose Thompson
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c463201d68
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Moved all rvvi files to rvvi directory.
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2024-07-23 13:03:21 -05:00 |
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Rose Thompson
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825dbefcb2
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Fixed bus width error. Have to check this FPGA to make sure this didn't break anything.
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2024-07-23 12:26:03 -05:00 |
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Rose Thompson
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bb74a0f96b
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Resolved more lint errors in the rvvi synthesized hardware.
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2024-07-23 12:23:04 -05:00 |
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Rose Thompson
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42f2469ea7
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Merge pull request #891 from davidharrishmc/dev
Increased covergen.py functional coverage to 87.6%
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2024-07-23 09:34:13 -05:00 |
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David Harris
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a4a0a10879
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Increased covergen.py functional coverage to 87.6%
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2024-07-23 04:38:13 -07:00 |
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Jordan Carlin
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36ffeb2dca
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Fix minimum scipy version for Ubuntu20.04
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2024-07-23 01:03:10 -07:00 |
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Jordan Carlin
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d096e2e4f8
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Fix python version for Ubuntu 20.04
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2024-07-23 00:16:27 -07:00 |
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Jordan Carlin
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e4c38dd766
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Add logs and reduce console output
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2024-07-22 23:13:38 -07:00 |
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Jordan Carlin
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d045fb6662
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Update python versions
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2024-07-22 23:12:48 -07:00 |
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Jordan Carlin
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16dd728ed6
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Use requirements file for pip packages
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2024-07-22 23:12:27 -07:00 |
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Jordan Carlin
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4e8cc68d3e
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Add DEBIAN_FRONTEND=noninteractive to apt
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2024-07-22 23:11:33 -07:00 |
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Jordan Carlin
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8c8e1a3fef
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Update section header function usage
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2024-07-22 23:10:45 -07:00 |
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Rose Thompson
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94a1ce32e7
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2024-07-22 17:48:34 -05:00 |
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Rose Thompson
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8ca565ed53
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Updated for a better ILA rvvi debugger.
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2024-07-22 17:44:04 -05:00 |
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Jacob Pease
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b05052311f
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Added sd_cmd and utility SPI functions.
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2024-07-22 16:57:04 -05:00 |
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Rose Thompson
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121342f4cc
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Updated the verilog-ethernet repo to remove most of the warnings. Updated the fpga constraints so the ILA is more useful when using RVVI.
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2024-07-22 16:12:06 -05:00 |
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Jacob Pease
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6a9141e3be
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Merge branch 'main' of github.com:openhwgroup/cvw into spiboot
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2024-07-22 13:06:05 -05:00 |
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Jacob Pease
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cec39fd3aa
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Added new SDC clock constraint.
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2024-07-22 13:05:16 -05:00 |
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Jacob Pease
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a506d76149
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Removed the old SDC. Added a second SPI peripheral that now will be used to control the SD card. SPI peripheral now outputs SPICLK. Removed references to the now non-existent external SDC in uncore. Removed all of the AXI Xilinx IP.
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2024-07-22 12:36:39 -05:00 |
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Rose Thompson
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00c30239bf
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Cleaned up rvvisynth.sv
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2024-07-22 12:22:41 -05:00 |
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Rose Thompson
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556c210e76
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Added option to use rvvi ila
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2024-07-22 12:19:37 -05:00 |
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