From 71883dca821feb7b603cd2359b9501e961034f8d Mon Sep 17 00:00:00 2001
From: Noah Boorstin <nboorstin@hmc.edu>
Date: Sat, 23 Jan 2021 17:52:05 -0500
Subject: [PATCH] More linux testbench fixes

So I'm super sorry for accidently overwriting the commits this morning
Need to be more careful with force pushing :(

This fixes the problem with CSRR somehow, by tying InstrAccessFaultF and
DataAccessFaultM to zero for now. I feel like this is not a good solution
and will cause problems in the future, but for the start it seems to work for now.
I'm fair certain we need these to accurately simulate to do linux properly.

Anyway, this super hackish solution is in place for now, now on to ignoring mispredicted reads
---
 wally-pipelined/src/testbench-busybear.sv |  6 +++++-
 wally-pipelined/wally-busybear.do         | 10 +++++-----
 2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/wally-pipelined/src/testbench-busybear.sv b/wally-pipelined/src/testbench-busybear.sv
index 0537fb23d..8fd14483c 100644
--- a/wally-pipelined/src/testbench-busybear.sv
+++ b/wally-pipelined/src/testbench-busybear.sv
@@ -15,6 +15,10 @@ module testbench_busybear #(parameter XLEN=64, MISA=32'h00000104, ZCSR = 1, ZCOU
   logic        InstrAccessFaultF, DataAccessFaultM;
   logic        TimerIntM, SwIntM; // from CLINT
   logic        ExtIntM = 0; // not yet connected
+
+  // for now, seem to need these to be zero until we get a better idea
+  assign InstrAccessFaultF = 0;
+  assign DataAccessFaultM = 0;
    
   // instantiate processor and memories
   wallypipelinedhart #(XLEN, MISA, ZCSR, ZCOUNTERS) dut(.ALUResultM(DataAdrM), .*);
@@ -101,7 +105,7 @@ module testbench_busybear #(parameter XLEN=64, MISA=32'h00000104, ZCSR = 1, ZCOU
     // then expected PC value
     scan_file_PC = $fscanf(data_file_PC, "%x\n", pcExpected);
     //check things!
-    if (PCF != pcExpected) begin
+    if (PCF !== pcExpected) begin
       $display("%t ps: PC does not equal PC expected: %x, %x", $time, PCF, pcExpected);
     //  $stop;
     end
diff --git a/wally-pipelined/wally-busybear.do b/wally-pipelined/wally-busybear.do
index 078127aa9..a52bda6a7 100644
--- a/wally-pipelined/wally-busybear.do
+++ b/wally-pipelined/wally-busybear.do
@@ -78,11 +78,11 @@ add wave -hex /testbench_busybear/dut/dp/regf/rf[29]
 add wave -hex /testbench_busybear/dut/dp/regf/rf[30]
 add wave -hex /testbench_busybear/dut/dp/regf/rf[31]
 add wave /testbench_busybear/InstrFName
-##add wave -hex /testbench_busybear/dut/dp/PCD
+add wave -hex /testbench_busybear/dut/dp/PCD
 #add wave -hex /testbench_busybear/dut/dp/InstrD
 add wave /testbench_busybear/InstrDName
 #add wave -divider
-##add wave -hex /testbench_busybear/dut/dp/PCE
+add wave -hex /testbench_busybear/dut/dp/PCE
 ##add wave -hex /testbench_busybear/dut/dp/InstrE
 add wave /testbench_busybear/InstrEName
 #add wave -hex /testbench_busybear/dut/dp/SrcAE
@@ -90,14 +90,14 @@ add wave /testbench_busybear/InstrEName
 #add wave -hex /testbench_busybear/dut/dp/ALUResultE
 #add wave /testbench_busybear/dut/dp/PCSrcE
 #add wave -divider
-##add wave -hex /testbench_busybear/dut/dp/PCM
+add wave -hex /testbench_busybear/dut/dp/PCM
 ##add wave -hex /testbench_busybear/dut/dp/InstrM
 add wave /testbench_busybear/InstrMName
 #add wave /testbench_busybear/dut/dmem/dtim/memwrite
 #add wave -hex /testbench_busybear/dut/dmem/AdrM
 #add wave -hex /testbench_busybear/dut/dmem/WriteDataM
 #add wave -divider
-#add wave -hex /testbench_busybear/dut/dp/PCW
+add wave -hex /testbench_busybear/dut/dp/PCW
 ##add wave -hex /testbench_busybear/dut/dp/InstrW
 add wave /testbench_busybear/InstrWName
 #add wave /testbench_busybear/dut/dp/RegWriteW
@@ -121,6 +121,6 @@ add wave /testbench_busybear/InstrWName
 #set DefaultRadix hexadecimal
 #
 #-- Run the Simulation 
-run 100
+run 300
 #run -all
 ##quit