Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Fixed bug with or_rows.

Browse Source 
If ROWS == 1 then the output was always X.  Fixed by adding if to check if ROWS==1.
This commit is contained in:
Ross Thompson 2021-09-11 15:51:11 -05:00
parent 3b12235954
commit 225657b8f9
1 changed files with 8 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
wally-pipelined/src/generic/or_rows.sv
View File

@ -36,10 +36,14 @@ module or_rows #(parameter ROWS = 8, COLS=2) (
logic [COLS-1:0] mid[ROWS-1:1];
genvar row, col;
generate
assign mid[1] = a[0] | a[1];
for (row=2; row < ROWS; row++)
assign mid[row] = mid[row-1] | a[row];
assign y = mid[ROWS-1];
if(ROWS == 1)
assign y = a[0];
else begin
assign mid[1] = a[0] | a[1];
for (row=2; row < ROWS; row++)
assign mid[row] = mid[row-1] | a[row];
assign y = mid[ROWS-1];
end
endgenerate
endmodule