diff --git a/wally-pipelined/src/generic/or_rows.sv b/wally-pipelined/src/generic/or_rows.sv
index c29528e48..f369c28c2 100644
--- a/wally-pipelined/src/generic/or_rows.sv
+++ b/wally-pipelined/src/generic/or_rows.sv
@@ -36,10 +36,14 @@ module or_rows #(parameter ROWS = 8, COLS=2) (
   logic [COLS-1:0] mid[ROWS-1:1];
   genvar row, col;
   generate
-    assign mid[1] = a[0] | a[1];
-    for (row=2; row < ROWS; row++)
-      assign mid[row] = mid[row-1] | a[row];
-    assign y = mid[ROWS-1];   
+    if(ROWS == 1)
+      assign y = a[0];
+    else begin
+      assign mid[1] = a[0] | a[1];
+      for (row=2; row < ROWS; row++)
+	assign mid[row] = mid[row-1] | a[row];
+      assign y = mid[ROWS-1];
+    end
    endgenerate
 endmodule