2021-11-30 00:32:51 +00:00
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dst := IP
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2021-12-03 16:05:13 +00:00
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all: FPGA
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2021-11-30 00:32:51 +00:00
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2021-12-03 16:05:13 +00:00
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FPGA: IP
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vivado -mode batch -source wally.tcl | tee wally.log
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IP: $(dst)/xlnx_proc_sys_reset.log \
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2021-11-30 00:32:51 +00:00
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$(dst)/xlnx_ddr4.log \
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$(dst)/xlnx_axi_clock_converter.log \
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$(dst)/xlnx_ahblite_axi_bridge.log
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$(dst)/%.log: %.tcl
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mkdir -p IP
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cd IP;\
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vivado -mode batch -source ../$*.tcl | tee $*.log
|
2021-11-30 00:42:28 +00:00
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2021-12-03 16:05:13 +00:00
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cleanIP:
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rm -rf IP
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cleanLogs:
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rm -rf *.jou *.log
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cleanFPGA:
|
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|
rm -rf WallyFPGA.* reports sim .Xil
|
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|
|
cleanAll: cleanIP cleanLogs cleanFPGA
|
