Ross Thompson 3d829dbbd3 Fixed two issues. ... First the xci files already include the xdc constraints for each IP block. There is no need to include the xdc files explicitly. Second the bidir buffer for the sd card was connected backwards.		2021-12-07 12:15:50 -06:00
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Makefile	Improved FPGA makefile and fixed timing constraints in clock converter.	2021-12-03 10:05:13 -06:00
wally.tcl	Fixed two issues.	2021-12-07 12:15:50 -06:00
xlnx_ahblite_axi_bridge.tcl	Created Makefile to manage IP generation.	2021-11-29 18:33:58 -06:00
xlnx_axi_clock_converter.tcl	Improved FPGA makefile and fixed timing constraints in clock converter.	2021-12-03 10:05:13 -06:00
xlnx_ddr4.tcl	Created Makefile to manage IP generation.	2021-11-29 18:33:58 -06:00
xlnx_proc_sys_reset.tcl	Created Makefile to manage IP generation.	2021-11-29 18:33:58 -06:00