forked from Github_Repos/cvw
74 lines
3.8 KiB
Systemverilog
74 lines
3.8 KiB
Systemverilog
///////////////////////////////////////////
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//
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// Written: David Harris
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// Modified: 11 September 2021
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//
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// Purpose: Recurrence-based SRT Division and Square Root
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module fpudivsqrtrecur (
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input logic clk,
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input logic reset,
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input logic FlushM, // flush the memory stage
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input logic StallM, // stall memory stage
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input logic FDivSqrtStart, // start a computation
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input logic FmtE, // precision 1 = double 0 = single
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input logic FDivE, FSqrtE,
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input logic [2:0] FrmM, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude
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input logic XSgnE, YSgnE, // input signs - execute stage
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input logic [`NE-1:0] XExpE, YExpE, // input exponents - execute stage
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input logic [`NF:0] XManE, YManE, // input mantissa - execute stage
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input logic XDenormE, YDenormE, // is denorm
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input logic XZeroE, YZeroE, // is zero - execute stage
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input logic XNaNE, YNaNE, // is NaN
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input logic XSNaNE, YSNaNE, // is signaling NaN
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input logic XInfE, YInfE, ZInfE, // is infinity
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input logic [10:0] BiasE, // bias (max exponent/2) ***parameterize in unpacking unit
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output logic FDviSqrtBusy, FDivSqrtDone, //currently occpied, or done with operation
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output logic [`FLEN-1:0] FDivSqrtResM, // result
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output logic [4:0] FDivSqrtFlgM // flags
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);
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logic FDivSqrtResSgn;
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logic [`FLEN-1:0] FDivSqrtRecurRes;
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// Radix-2 SRT Division and Square Root
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// Special Cases
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// *** shift to handle denorms in hardware
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assign FDivSqrtResSgn = FDivE & (XSgnE ^ YSgnE); // Sign is negative for division if inputs have opposite signs
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always_comb begin
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if (FSqrtE & XSgnE | FDivE & XZeroE & YZeroE | XNaNE | FDivE & YNaNE) FDivSqrtResM = 0; // ***replace with NAN; // *** which one
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else if (FDivE & YZeroE | XInfE) FDivSqrtResM = {FDivSqrtResSgn, (`NE)'(1), (`NF)'(0)}; // infinity
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else if (FDivE & YInfE) FDivSqrtResM = {FDivSqrtResSgn, (`NE)'(0), (`NF)'(0)}; // zero
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else FDivSqrtResM = FDivSqrtRecurRes;
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end
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// *** handle early termination in the special cases
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// *** handle signaling NANs
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endmodule |