cvw/wally-pipelined/src
Ross Thompson 66e84f3a2c Merge branch 'bp' into main
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
2021-03-04 13:35:46 -06:00
..
dmem Install dtlb in dmem 2021-03-04 03:30:06 -05:00
ebu Cleaned out unused signals 2021-02-26 09:17:36 -05:00
fpu Retimed peripherals for AHB interface 2021-02-26 00:55:41 -05:00
generic Initial (untested) implementation of lr and sc 2021-03-01 00:09:45 -05:00
hazard Merge branch 'bp' into main 2021-03-04 13:35:46 -06:00
ieu Merge branch 'bp' into main 2021-03-04 13:35:46 -06:00
ifu Merge branch 'bp' into main 2021-03-04 13:35:46 -06:00
mmu Install tlb into ifu 2021-03-04 03:11:34 -05:00
muldiv Cleaned out unused signals 2021-02-26 09:17:36 -05:00
privileged Eliminated flushing pipeline on CSR reads 2021-02-26 17:00:07 -05:00
tlb_toy Install tlb into ifu 2021-03-04 03:11:34 -05:00
uncore Fix to 32-bit option of commit babe6ce9db 2021-03-04 01:33:34 -06:00
wally Merge branch 'bp' into main 2021-03-04 13:35:46 -06:00