David Harris 9de97c1e20 Fixed busybear by restoring InstrValidW needed by testbench		2021-07-13 14:17:36 -04:00
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cache	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-07-04 18:55:24 -04:00
ebu	Gave names to for loops in generate blocks for ease of reference	2021-07-04 18:52:16 -04:00
fpu	Fixed writting MStatus FS bits	2021-07-13 13:20:30 -04:00
generic	added or.sv	2021-07-13 13:26:40 -04:00
hazard	Merge branch 'main' into bigbadbranch	2021-07-02 11:52:26 -05:00
ieu	Fixed busybear by restoring InstrValidW needed by testbench	2021-07-13 14:17:36 -04:00
ifu	MMU produces page fault when upper bits aren't equal. Renamed input to MMU to be 'Address' and moved translation mux into MMU out of TLB	2021-07-06 15:29:42 -04:00
lsu	MMU produces page fault when upper bits aren't equal. Renamed input to MMU to be 'Address' and moved translation mux into MMU out of TLB	2021-07-06 15:29:42 -04:00
mmu	Replaced .or with or_rows structural code in MMU read circuitry for synthesis.	2021-07-13 09:32:02 -04:00
muldiv	Fixed disabling MulDiv when not supported. Started adding generate for FPU unsupported	2021-07-04 19:33:46 -04:00
privileged	Fixed writting MStatus FS bits	2021-07-13 13:22:04 -04:00
uncore	Simplified PLIC with generate	2021-07-04 19:17:15 -04:00
wally	Fixed writting MStatus FS bits	2021-07-13 13:22:04 -04:00