Ross Thompson c6ebe7733b Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary. ... About 149307ns of simulation run.		2021-02-18 21:32:15 -06:00
..
dmem	Rename ifu/dmem/ebu signals to match uarch diagram	2021-02-02 15:09:24 -05:00
ebu	Rename ifu/dmem/ebu signals to match uarch diagram	2021-02-02 15:09:24 -05:00
fpu/build_temp	Parallel FSR's and F CTRL logic	2021-02-04 02:25:55 -06:00
generic	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00
hazard	Integrated the branch predictor into the hardward. Not yet working.	2021-02-17 22:19:17 -06:00
ieu	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-02-02 19:44:43 -05:00
ifu	Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary.	2021-02-18 21:32:15 -06:00
privileged	Minor tweaks	2021-02-02 19:44:37 -05:00
uncore	bus rw bugfix and peripherals testing	2021-02-12 00:02:45 -05:00
wally	Integrated the branch predictor into the hardward. Not yet working.	2021-02-17 22:19:17 -06:00