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Configurable RISC-V Processor
15 Commits 14 Branches 1 Tag 31 MiB
Assembly 55.4%
C 27.2%
SystemVerilog 8.2%
Python 2.7%
Stata 2.3%
Other 4.2%
e8132800d3
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Noah Boorstin e8132800d3 Start of gdb output parser 
super simple rn, just getting instructions, will get registers soon
2021-01-22 13:57:58 -05:00
riscv-o3@afb27bd558 Initial Checkin 2021-01-14 23:37:51 -05:00
wally-pipelined More testbench setup work 2021-01-21 17:55:05 -05:00
.gitignore More testbench setup work 2021-01-21 17:55:05 -05:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor