Ross Thompson 4322694f7a Switch to use RV64IC for the benchmarks. ... Still not working correctly with the icache. instr addr correct got		2021-04-07 19:12:43 -05:00
..
cache	Give some cache mem inputs a better name	2021-03-24 12:31:50 -04:00
dmem	Connect tlb, pagetablewalker, and memory	2021-03-18 14:35:46 -04:00
ebu	Finish finite state machines for page table walker	2021-03-25 02:48:40 -04:00
fpu	FPU Pipeline completed - can begin integration	2021-03-25 13:29:03 -05:00
generic	change flop in ahb controller to use normal flop module	2021-03-10 19:14:02 +00:00
hazard	Merge upstream changes	2021-03-09 21:20:34 -05:00
ieu	Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.	2021-03-30 23:18:20 -05:00
ifu	Merge branch 'icache_bp_bug' into tests	2021-04-06 21:46:40 -05:00
mmu	Connect tlb, pagetablewalker, and memory	2021-03-18 14:35:46 -04:00
muldiv	Cleaned out unused signals	2021-02-26 09:17:36 -05:00
privileged	Merge branch 'icache_bp_bug' into tests	2021-04-06 21:46:40 -05:00
tlb_toy	Install tlb into ifu	2021-03-04 03:11:34 -05:00
uncore	Switch to use RV64IC for the benchmarks.	2021-04-07 19:12:43 -05:00
wally	Merge branch 'icache_bp_bug' into tests	2021-04-06 21:46:40 -05:00