cvw/pipelined/src/fpu
2023-01-07 05:34:58 -08:00
..
fdivsqrt renamed alot of signals in fpu 2023-01-06 10:35:23 -06:00
fma renamed alot of signals in fpu 2023-01-06 10:35:23 -06:00
postproc renamed alot of signals in fpu 2023-01-06 10:35:23 -06:00
fclassify.sv renamed alot of signals in fpu 2023-01-06 10:35:23 -06:00
fcmp.sv Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00
fctrl.sv Fixed floating Sqrt signal when floating point is disabled, causing REMU tohang during buildroot around 3.2M 2022-12-27 21:24:38 -08:00
fcvt.sv vclean working; started removing unused signals 2023-01-07 05:34:58 -08:00
fhazard.sv Removed XEnE, YEnE, and ZEnE from forward logic. 2022-12-23 14:27:03 -06:00
fpu.sv vclean working; started removing unused signals 2023-01-07 05:34:58 -08:00
fregfile.sv Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00
fsgninj.sv Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00
unpack.sv renamed alot of signals in fpu 2023-01-06 10:35:23 -06:00
unpackinput.sv renamed alot of signals in fpu 2023-01-06 10:35:23 -06:00