forked from Github_Repos/cvw
42c0a10d07
FlushW prevents writting the cache, dtim, and bus state. FlushW still gates HTRANS. FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to not stall W if we get a trap.
102 lines
4.5 KiB
Systemverilog
102 lines
4.5 KiB
Systemverilog
///////////////////////////////////////////
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// spillsupport.sv
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//
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// Written: Ross Thompson ross1728@gmail.com January 28, 2022
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// Modified:
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//
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// Purpose: allows the IFU to make extra memory request if instruction address crosses
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// cache line boundaries or if instruction address without a cache crosses
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// XLEN/8 boundary.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module spillsupport #(parameter CACHE_ENABLED)
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(input logic clk,
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input logic reset,
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input logic StallF, Flush,
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input logic [`XLEN-1:0] PCF,
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input logic [`XLEN-3:0] PCPlusUpperF,
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input logic [`XLEN-1:0] PCNextF,
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input logic [31:0] InstrRawF,
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input logic IFUCacheBusStallF,
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input logic ITLBMissF,
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input logic InstrDAPageFaultF,
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output logic [`XLEN-1:0] PCNextFSpill,
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output logic [`XLEN-1:0] PCFSpill,
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output logic SelNextSpillF,
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output logic [31:0] PostSpillInstrRawF,
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output logic CompressedF);
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localparam integer SPILLTHRESHOLD = CACHE_ENABLED ? `ICACHE_LINELENINBITS/32 : 1;
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logic [`XLEN-1:0] PCPlus2F;
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logic TakeSpillF;
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logic SpillF;
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logic SelSpillF, SpillSaveF;
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logic [15:0] SpillDataLine0, SavedInstr;
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typedef enum logic [1:0] {STATE_READY, STATE_SPILL} statetype;
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(* mark_debug = "true" *) statetype CurrState, NextState;
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mux2 #(`XLEN) pcplus2mux(.d0({PCF[`XLEN-1:2], 2'b10}), .d1({PCPlusUpperF, 2'b00}),
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.s(PCF[1]), .y(PCPlus2F));
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mux2 #(`XLEN) pcnextspillmux(.d0(PCNextF), .d1(PCPlus2F), .s(SelNextSpillF & ~Flush),
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.y(PCNextFSpill));
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mux2 #(`XLEN) pcspillmux(.d0(PCF), .d1(PCPlus2F), .s(SelSpillF), .y(PCFSpill));
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assign SpillF = &PCF[$clog2(SPILLTHRESHOLD)+1:1];
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assign TakeSpillF = SpillF & ~IFUCacheBusStallF & ~(ITLBMissF | (`HPTW_WRITES_SUPPORTED & InstrDAPageFaultF));
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always_ff @(posedge clk)
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if (reset | Flush) CurrState <= #1 STATE_READY;
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else CurrState <= #1 NextState;
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always_comb begin
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case (CurrState)
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STATE_READY: if (TakeSpillF) NextState = STATE_SPILL;
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else NextState = STATE_READY;
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STATE_SPILL: if(IFUCacheBusStallF | StallF) NextState = STATE_SPILL;
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else NextState = STATE_READY;
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default: NextState = STATE_READY;
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endcase
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end
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assign SelSpillF = (CurrState == STATE_SPILL);
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assign SelNextSpillF = (CurrState == STATE_READY & TakeSpillF) |
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(CurrState == STATE_SPILL & IFUCacheBusStallF);
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assign SpillSaveF = (CurrState == STATE_READY) & TakeSpillF;
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assign SavedInstr = CACHE_ENABLED ? InstrRawF[15:0] : InstrRawF[31:16];
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flopenr #(16) SpillInstrReg(.clk(clk),
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.en(SpillSaveF & ~Flush),
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.reset(reset),
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.d(SavedInstr),
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.q(SpillDataLine0));
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mux2 #(32) postspillmux(.d0(InstrRawF), .d1({InstrRawF[15:0], SpillDataLine0}), .s(SpillF),
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.y(PostSpillInstrRawF));
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assign CompressedF = PostSpillInstrRawF[1:0] != 2'b11;
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endmodule
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