Alec Vercruysse 6299c0ef0b Cacheway Exclude FlushStage=1 when SetValidWay=1 ... We determined that this case is not hit even for i$, so this case is also excluded separately for i$. It could be a better idea to remove the ~FlushStage check completely (if we're sure). My reasoning for this one is written as a comment in the exclusion script: since a pipeline stall is asserted by the cache in the fetch stage (which happens before going into the WRITE_LINE state and asserting SetValidWay), there seems to be no way to trigger a FlushStage (FlushW for D$) while the stallM is active.		2023-04-25 20:30:46 -07:00
..
slack-notifier
wave-dos
bpred-sim.py
buildrootBugFinder.py
coverage-exclusions-rv64gc.do
fpga-wave.do
GetLineNum.do
imperas.ic	Turned on SVADU_SUPPORTED in rv32/64gc wally-config and in imperas.ic. ImperasDV is happy with these privileged tests now	2023-04-10 07:05:06 -07:00
lint-wally
linux-wave.do
make-tests.sh
Makefile
makefile-memfile
regression-wally
run-imperas-linux.sh
run-imperasdv-tests.bash
rv64gc_CacheSim.py
sim-buildroot
sim-buildroot-batch
sim-imperas	Cleaned up branch predictor performance counters.	2023-03-01 17:05:42 -06:00
sim-testfloat
sim-testfloat-batch
sim-wally
sim-wally-batch
test
testfloat.do
wally-batch.do
wally-imperas-cov.do
wally-imperas-no-idv.do
wally-imperas.do
wally-linux-imperas.do
wally.do
wave-all.do
wave-fpu.do
wave.do	Updated testbench to record coremark performance counters.	2023-03-08 17:11:27 -06:00