forked from Github_Repos/cvw
104 lines
5.1 KiB
Systemverilog
104 lines
5.1 KiB
Systemverilog
///////////////////////////////////////////
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// fdivsqrt.sv
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//
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// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu, amaiuolo@hmc.edu
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// Modified:13 January 2022
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//
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// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
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//
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// Documentation: RISC-V System on Chip Design Chapter 13
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module fdivsqrt(
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input logic clk,
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input logic reset,
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input logic [`FMTBITS-1:0] FmtE,
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input logic XsE,
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input logic [`NF:0] XmE, YmE,
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input logic [`NE-1:0] XeE, YeE,
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input logic XInfE, YInfE,
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input logic XZeroE, YZeroE,
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input logic XNaNE, YNaNE,
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input logic FDivStartE, IDivStartE,
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input logic StallM,
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input logic FlushE,
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input logic SqrtE, SqrtM,
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input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // these are the src outputs before the mux choosing between them and PCE to put in srcA/B
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input logic [2:0] Funct3E, Funct3M,
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input logic IntDivE, W64E,
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output logic DivStickyM,
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output logic FDivBusyE, IFDivStartE, FDivDoneE,
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output logic [`NE+1:0] QeM,
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output logic [`DIVb:0] QmM,
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output logic [`XLEN-1:0] FIntDivResultM
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);
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// Floating-point division and square root module, with optional integer division and remainder
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// Computes X/Y, sqrt(X), A/B, or A%B
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logic [`DIVb+3:0] WS, WC; // Partial remainder components
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logic [`DIVb+3:0] X; // Iterator Initial Value (from dividend)
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logic [`DIVb-1:0] DPreproc, D; // Iterator Divisor
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logic [`DIVb:0] FirstU, FirstUM; // Intermediate result values
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logic [`DIVb+1:0] FirstC; // Step tracker
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logic Firstun; // Quotient selection
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logic WZeroE; // Early termination flag
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logic SpecialCaseM; // Divide by zero, square root of negative, etc.
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logic DivStartE; // Enable signal for flops during stall
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// Integer div/rem signals
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logic BZeroM; // Denominator is zero
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logic IntDivM; // Integer operation
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logic [`DIVBLEN:0] nE, nM, mM; // Shift amounts
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logic NegQuotM, ALTBM, AsM, W64M; // Special handling for postprocessor
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logic [`XLEN-1:0] AM; // Original Numerator for postprocessor
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logic ISpecialCaseE; // Integer div/remainder special cases
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fdivsqrtpreproc fdivsqrtpreproc( // Preprocessor
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.clk, .IFDivStartE, .Xm(XmE), .Ym(YmE), .Xe(XeE), .Ye(YeE),
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.Fmt(FmtE), .Sqrt(SqrtE), .XZeroE, .Funct3E,
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.QeM, .X, .DPreproc,
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// Int-specific
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.ForwardedSrcAE, .ForwardedSrcBE, .IntDivE, .W64E, .ISpecialCaseE,
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.nE, .BZeroM, .nM, .mM, .AM,
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.IntDivM, .W64M, .NegQuotM, .ALTBM, .AsM);
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fdivsqrtfsm fdivsqrtfsm( // FSM
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.clk, .reset, .FmtE, .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE,
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.FDivStartE, .XsE, .SqrtE, .WZeroE, .FlushE, .StallM,
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.FDivBusyE, .IFDivStartE, .FDivDoneE, .SpecialCaseM,
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// Int-specific
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.IDivStartE, .ISpecialCaseE, .nE, .IntDivE);
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fdivsqrtiter fdivsqrtiter( // CSA Iterator
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.clk, .IFDivStartE, .FDivBusyE, .SqrtE, .X, .DPreproc,
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.D, .FirstU, .FirstUM, .FirstC, .Firstun, .FirstWS(WS), .FirstWC(WC));
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fdivsqrtpostproc fdivsqrtpostproc( // Postprocessor
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.clk, .reset, .StallM, .WS, .WC, .D, .FirstU, .FirstUM, .FirstC,
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.SqrtE, .Firstun, .SqrtM, .SpecialCaseM,
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.QmM, .WZeroE, .DivStickyM,
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// Int-specific
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.nM, .mM, .ALTBM, .AsM, .BZeroM, .NegQuotM, .W64M, .RemOpM(Funct3M[1]), .AM,
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.FIntDivResultM);
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endmodule
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