Ross Thompson cd0da2e3b3 Updated the names of the *WriteDataM inside the LSU to more meaningful names. ... Moved the FWriteDataMux so that the bus and dtim both get fpu stores. Modified the PMA to disallow double sized reads when XLEN=32.		2022-08-23 10:34:39 -05:00
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adrdec.sv	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
adrdecs.sv	Updated the names of the *WriteDataM inside the LSU to more meaningful names.	2022-08-23 10:34:39 -05:00
hptw.sv	Removed FStore2 and simplified HPTW	2022-08-22 13:29:54 -07:00
mmu.sv	Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB.	2022-03-24 23:47:28 -05:00
pmachecker.sv	Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.	2022-01-27 17:11:27 -06:00
pmpadrdec.sv	took first match out of pmpadrdec	2022-07-06 00:02:01 +00:00
pmpchecker.sv	took first match out of pmpadrdec	2022-07-06 00:02:01 +00:00
tlb.sv	Broken state. address translation not working after changes to hptw to support atomic updates to PT.	2022-02-16 23:37:36 -06:00
tlbcam.sv	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
tlbcamline.sv	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
tlbcontrol.sv	Removing unused signals	2022-05-12 14:36:15 +00:00
tlblru.sv	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
tlbmixer.sv	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
tlbram.sv	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
tlbramline.sv	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00