Ross Thompson cd0da2e3b3 Updated the names of the *WriteDataM inside the LSU to more meaningful names. ... Moved the FWriteDataMux so that the bus and dtim both get fpu stores. Modified the PMA to disallow double sized reads when XLEN=32.		2022-08-23 10:34:39 -05:00
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config	LSU minor edits	2022-08-23 07:35:47 -07:00
misc	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
regression	Changed signal names.	2022-08-17 16:12:04 -05:00
src	Updated the names of the *WriteDataM inside the LSU to more meaningful names.	2022-08-23 10:34:39 -05:00
srt	divider sizes reworked to match book	2022-07-22 22:02:04 +00:00
testbench	LSU minor edits	2022-08-23 07:35:47 -07:00