Ross Thompson 42c0a10d07 Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU). ... FlushW prevents writting the cache, dtim, and bus state. FlushW still gates HTRANS. FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to not stall W if we get a trap.		2022-11-07 15:50:55 -06:00
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wallypipelinedcore.sv	Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU).	2022-11-07 15:50:55 -06:00
wallypipelinedsoc.sv	FIxed wallypipelinedsoc merge conflict	2022-08-25 15:36:47 -07:00
wallypipelinedsocwrapper.v	Removed logic from Verilog wrapper.	2022-08-21 14:07:43 -05:00