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cvw/synthDC
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Madeleine Masser-Frye ca65ca2877 organized ppa files into ppa directory
2022-07-05 22:28:25 +00:00
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ppa organized ppa files into ppa directory 2022-07-05 22:28:25 +00:00
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.synopsys_dc.setup added support for tsmc28, fixed ff modules/analysis for timing 2022-05-25 06:44:22 +00:00
extractSummary.py update wally synth analysis 2022-06-28 02:28:13 +00:00
Makefile make clean rm extra files 2022-06-28 02:23:29 +00:00
README.md Slight tweaks to synthDC for library variables 2022-02-10 17:56:27 -06:00
runAllSynths.sh make clean rm extra files 2022-06-28 02:23:29 +00:00
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README.md

Synthesis for RISC-V Microprocessor System-on-Chip Design

This subdirectory contains synthesis scripts for use with Synopsys (snps) Design Compiler (DC). Synthesis commands are found in scripts/synth.tcl.

Example Usage make synth DESIGN=wallypipelinedcore FREQ=500

environment variables

DESIGN Design provides the name of the output log. Default is synth.

FREQ Frequency in MHz. Default is 500

CONFIG The Wally configuration file. The default is rv32e. Examples: rv32e, rv64gc, rv32gc

TECH The target standard cell library. The default is sky130. sky90: skywater 90nm TT 25C sky130: skywater 130nm TT 25C

SAIFPOWER Controls if power analysis is driven by switching factor or RTL modelsim simulation. When enabled requires a saif file named power.saif. The default is 0. 0: switching factor power analysis 1: RTL simulation driven power analysis.