Katherine Parry c9180f4ebd FDIV and FSQRT passes when simulating in modelsim		2021-07-18 23:00:04 -04:00
..
cache	Fixed LRSC in 64bit version. 32bit version is broken.	2021-07-17 20:58:49 -05:00
ebu	moved subwordread to lsu	2021-07-17 20:37:20 -04:00
fpu	FDIV and FSQRT passes when simulating in modelsim	2021-07-18 23:00:04 -04:00
generic	renamed or_rows.sv	2021-07-16 20:17:03 -04:00
hazard	Renamed DCacheStall to LSUStall in hart and hazard.	2021-07-15 10:16:16 -05:00
ieu	Merge branch 'main' into dcache	2021-07-15 11:55:20 -05:00
ifu	hptw: Propagating PageTableEntryF removal through IFU	2021-07-17 15:04:39 -04:00
lsu	Renamed pagetablewalker to hptw	2021-07-18 04:11:33 -04:00
mmu	Added FLEN, NE, NF to config and started using these in FMA1	2021-07-18 17:28:25 -04:00
muldiv	Fixed disabling MulDiv when not supported. Started adding generate for FPU unsupported	2021-07-04 19:33:46 -04:00
privileged	trap.sv comment cleanup	2021-07-17 16:01:07 -04:00
uncore	Simplified PLIC with generate	2021-07-04 19:17:15 -04:00
wally	hptw: Removed NonBusTrapM from LSU	2021-07-17 15:22:24 -04:00