Ross Thompson c91436d3b7 Merge branch 'icache_bp_bug' into tests ... Not sure this merge is right.		2021-04-06 21:46:40 -05:00
..
bpred.sv	Merge remote-tracking branch 'refs/remotes/origin/tests' into tests	2021-04-06 21:20:55 -05:00
BTBPredictor.sv	Corrected a number of bugs in the branch predictor.	2021-03-31 11:54:02 -05:00
decompress.sv	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00
globalHistoryPredictor.sv	added localHistoryPredictor	2021-04-01 22:22:40 +05:30
gshare.sv	Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.	2021-03-30 23:18:20 -05:00
icache.sv	Fix another bug in icache	2021-04-06 17:47:00 -04:00
ifu.sv	Merge branch 'icache_bp_bug' into tests	2021-04-06 21:46:40 -05:00
localHistoryPredictor.sv	fixed minor bugs in localHistory	2021-04-01 13:40:08 -04:00
RAsPredictor.sv	Corrected a number of bugs in the branch predictor.	2021-03-31 11:54:02 -05:00
satCounter2.sv	We now have a solid rough draft of the 2 bit sat counter branch predictor with BTB and RAS.	2021-02-15 14:51:39 -06:00
SramModel.sv	Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary.	2021-02-18 21:32:15 -06:00
twoBitPredictor.sv	Fixed forwarding around the 2 bit predictor.	2021-03-04 13:01:41 -06:00