forked from Github_Repos/cvw
120 lines
4.2 KiB
Systemverilog
120 lines
4.2 KiB
Systemverilog
///////////////////////////////////////////
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// dtim.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Data tightly integrated memory
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module dtim #(parameter BASE=0, RANGE = 65535) (
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input logic HCLK, HRESETn,
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input logic HSELTim,
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input logic [31:0] HADDR,
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input logic HWRITE,
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input logic HREADY,
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input logic [1:0] HTRANS,
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input logic [`XLEN-1:0] HWDATA,
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output logic [`XLEN-1:0] HREADTim,
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output logic HRESPTim, HREADYTim
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);
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localparam MemStartAddr = BASE>>(1+`XLEN/32);
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localparam MemEndAddr = (RANGE+BASE)>>1+(`XLEN/32);
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logic [`XLEN-1:0] RAM[BASE>>(1+`XLEN/32):(RANGE+BASE)>>1+(`XLEN/32)];
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logic [31:0] HWADDR, A;
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logic [`XLEN-1:0] HREADTim0;
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// logic [`XLEN-1:0] write;
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logic prevHREADYTim, risingHREADYTim;
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logic initTrans;
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logic [15:0] entry;
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logic memread, memwrite;
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logic [3:0] busycount;
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assign initTrans = HREADY & HSELTim & (HTRANS != 2'b00);
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// *** this seems like a weird way to use reset
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flopenr #(1) memreadreg(HCLK, 1'b0, initTrans | ~HRESETn, HSELTim & ~HWRITE, memread);
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flopenr #(1) memwritereg(HCLK, 1'b0, initTrans | ~HRESETn, HSELTim & HWRITE, memwrite);
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flopenr #(32) haddrreg(HCLK, 1'b0, initTrans | ~HRESETn, HADDR, A);
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// busy FSM to extend READY signal
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always_ff @(posedge HCLK, negedge HRESETn)
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if (~HRESETn) begin
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busycount <= 0;
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HREADYTim <= #1 0;
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end else begin
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if (initTrans) begin
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busycount <= 0;
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HREADYTim <= #1 0;
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end else if (~HREADYTim) begin
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if (busycount == 0) begin // TIM latency, for testing purposes. *** test with different values such as 2
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HREADYTim <= #1 1;
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end else begin
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busycount <= busycount + 1;
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end
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end
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end
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assign HRESPTim = 0; // OK
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// Rising HREADY edge detector
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// Indicates when dtim is finishing up
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// Needed because HREADY may go high for other reasons,
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// and we only want to write data when finishing up.
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flopr #(1) prevhreadytimreg(HCLK,~HRESETn,HREADYTim,prevHREADYTim);
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assign risingHREADYTim = HREADYTim & ~prevHREADYTim;
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// Model memory read and write
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/* -----\/----- EXCLUDED -----\/-----
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integer index;
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initial begin
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for(index = MemStartAddr; index < MemEndAddr; index = index + 1) begin
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RAM[index] <= {`XLEN{1'b0}};
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end
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end
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-----/\----- EXCLUDED -----/\----- */
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/* verilator lint_off WIDTH */
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generate
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if (`XLEN == 64) begin
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always_ff @(posedge HCLK) begin
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HWADDR <= #1 A;
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HREADTim0 <= #1 RAM[A[31:3]];
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if (memwrite & risingHREADYTim) RAM[HWADDR[31:3]] <= #1 HWDATA;
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end
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end else begin
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always_ff @(posedge HCLK) begin
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HWADDR <= #1 A;
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HREADTim0 <= #1 RAM[A[31:2]];
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if (memwrite & risingHREADYTim) RAM[HWADDR[31:2]] <= #1 HWDATA;
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end
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end
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endgenerate
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/* verilator lint_on WIDTH */
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assign HREADTim = HREADYTim ? HREADTim0 : `XLEN'bz;
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endmodule
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