forked from Github_Repos/cvw
17 lines
428 B
Systemverilog
17 lines
428 B
Systemverilog
parameter cvw_t P = '{
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PA_BITS : PA_BITS,
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XLEN: XLEN,
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AHBW: AHBW,
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MISA: MISA,
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BUS_SUPPORTED: BUS_SUPPORTED,
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ZICSR_SUPPORTED: ZICSR_SUPPORTED,
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M_SUPPORTED: M_SUPPORTED,
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ZMMUL_SUPPORTED: ZMMUL_SUPPORTED,
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F_SUPPORTED: F_SUPPORTED,
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PMP_ENTRIES: PMP_ENTRIES,
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LLEN: LLEN,
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FPGA: FPGA,
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QEMU: QEMU,
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VPN_SEGMENT_BITS: VPN_SEGMENT_BITS,
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FLEN: FLEN
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}; |