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parameterized top-level module

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This commit is contained in:
David Harris 2023-03-24 11:00:40 -07:00
parent a5e569245b
commit c552db5350
9 changed files with 516 additions and 95 deletions
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177
config/rv32e/rv32e-config.vh Normal file
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@ -0,0 +1,177 @@
//////////////////////////////////////////
// wally-config.vh
//
// Written: David_Harris@hmc.edu 4 January 2021
// Modified:
//
// Purpose: Specify which features are configured
// Macros to determine which modes are supported based on MISA
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
localparam PA_BITS = 34;
localparam AHBW = 32;
localparam XLEN = 32;
localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 );
localparam BUS_SUPPORTED = 1'b1;
localparam ZICSR_SUPPORTED = 1'b0;
localparam M_SUPPORTED = 1'b0;
localparam ZMMUL_SUPPORTED = 1'b0;
localparam F_SUPPORTED = 1'b0;
localparam PMP_ENTRIES = 0;
localparam LLEN = 32;
localparam FPGA = 1'b0;
localparam QEMU = 1'b0;
// //VPN_SEGMENT_BITS: (LLEN == 32 ? 10 : 9),
// `include "test-shared.vh"
localparam FLEN = 32;
`include "test-shared.vh"
/*
// include shared configuration
`include "wally-shared.vh"
`define FPGA 0
`define QEMU 0
// RV32 or RV64: XLEN = 32 or 64
`define XLEN 32
// IEEE 754 compliance
`define IEEE754 0
// E
`define MISA (32'h00000010)
`define ZICSR_SUPPORTED 0
`define ZIFENCEI_SUPPORTED 0
`define COUNTERS 0
`define ZICOUNTERS_SUPPORTED 0
`define ZFH_SUPPORTED 0
`define SSTC_SUPPORTED 0
// LSU microarchitectural Features
`define BUS_SUPPORTED 1
`define DCACHE_SUPPORTED 0
`define ICACHE_SUPPORTED 0
`define VIRTMEM_SUPPORTED 0
`define VECTORED_INTERRUPTS_SUPPORTED 0
`define BIGENDIAN_SUPPORTED 0
// TLB configuration. Entries should be a power of 2
`define ITLB_ENTRIES 0
`define DTLB_ENTRIES 0
// Cache configuration. Sizes should be a power of two
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
`define DCACHE_NUMWAYS 4
`define DCACHE_WAYSIZEINBYTES 4096
`define DCACHE_LINELENINBITS 512
`define ICACHE_NUMWAYS 4
`define ICACHE_WAYSIZEINBYTES 4096
`define ICACHE_LINELENINBITS 512
// Integer Divider Configuration
// IDIV_BITSPERCYCLE must be 1, 2, or 4
`define IDIV_BITSPERCYCLE 1
`define IDIV_ON_FPU 0
// Legal number of PMP entries are 0, 16, or 64
`define PMP_ENTRIES 0
// Address space
`define RESET_VECTOR 32'h80000000
// WFI Timeout Wait
`define WFI_TIMEOUT_BIT 16
// Peripheral Addresses
// Peripheral memory space extends from BASE to BASE+RANGE
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
`define DTIM_SUPPORTED 1'b0
`define DTIM_BASE 34'h80000000
`define DTIM_RANGE 34'h007FFFFF
`define IROM_SUPPORTED 1'b0
`define IROM_BASE 34'h80000000
`define IROM_RANGE 34'h007FFFFF
`define BOOTROM_SUPPORTED 1'b1
`define BOOTROM_BASE 34'h00001000
`define BOOTROM_RANGE 34'h00000FFF
`define UNCORE_RAM_SUPPORTED 1'b1
`define UNCORE_RAM_BASE 34'h80000000
`define UNCORE_RAM_RANGE 34'h07FFFFFF
`define EXT_MEM_SUPPORTED 1'b0
`define EXT_MEM_BASE 34'h80000000
`define EXT_MEM_RANGE 34'h07FFFFFF
`define CLINT_SUPPORTED 1'b0
`define CLINT_BASE 34'h02000000
`define CLINT_RANGE 34'h0000FFFF
`define GPIO_SUPPORTED 1'b0
`define GPIO_BASE 34'h10060000
`define GPIO_RANGE 34'h000000FF
`define UART_SUPPORTED 1'b0
`define UART_BASE 34'h10000000
`define UART_RANGE 34'h00000007
`define PLIC_SUPPORTED 1'b0
`define PLIC_BASE 34'h0C000000
`define PLIC_RANGE 34'h03FFFFFF
`define SDC_SUPPORTED 1'b0
`define SDC_BASE 34'h00012100
`define SDC_RANGE 34'h0000001F
// Bus Interface width
`define AHBW 32
// Test modes
// Tie GPIO outputs back to inputs
`define GPIO_LOOPBACK_TEST 1
// Hardware configuration
`define UART_PRESCALE 1
// Interrupt configuration
`define PLIC_NUM_SRC 10
// comment out the following if >=32 sources
`define PLIC_NUM_SRC_LT_32
`define PLIC_GPIO_ID 3
`define PLIC_UART_ID 10
`define BPRED_SUPPORTED 0
`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
`define BPRED_SIZE 10
`define BTB_SIZE 10
`define SVADU_SUPPORTED 0
`define ZMMUL_SUPPORTED 0
// FPU division architecture
`define RADIX 32'h4
`define DIVCOPIES 32'h4
// bit manipulation
`define ZBA_SUPPORTED 0
`define ZBB_SUPPORTED 0
`define ZBC_SUPPORTED 0
`define ZBS_SUPPORTED 0
// Memory synthesis configuration
`define USE_SRAM 0
*/

17
config/shared/parameter-defs.vh Normal file
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@ -0,0 +1,17 @@
parameter cvw_t P = '{
PA_BITS : PA_BITS,
XLEN: XLEN,
AHBW: AHBW,
MISA: MISA,
BUS_SUPPORTED: BUS_SUPPORTED,
ZICSR_SUPPORTED: ZICSR_SUPPORTED,
M_SUPPORTED: M_SUPPORTED,
ZMMUL_SUPPORTED: ZMMUL_SUPPORTED,
F_SUPPORTED: F_SUPPORTED,
PMP_ENTRIES: PMP_ENTRIES,
LLEN: LLEN,
FPGA: FPGA,
QEMU: QEMU,
VPN_SEGMENT_BITS: VPN_SEGMENT_BITS,
FLEN: FLEN
};

2
config/shared/test-shared.vh Normal file
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@ -0,0 +1,2 @@
localparam VPN_SEGMENT_BITS = (LLEN == 32 ? 10 : 9);

22
sim/lint-wally_32e Executable file
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@ -0,0 +1,22 @@
#!/bin/bash
# check for warnings in Verilog code
# The verilator lint tool is faster and better than Modelsim so it is best to run this first.
export PATH=$PATH:/usr/local/bin/
verilator=`which verilator`
basepath=$(dirname $0)/..
for config in rv32e; do
#for config in rv64gc; do
echo "$config linting..."
if !($verilator --lint-only "$@" --top-module wallypipelinedsoc_32e "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
echo "Exiting after $config lint due to errors or warnings"
exit 1
fi
done
echo "All lints run with no errors or warnings"
# --lint-only just runs lint rather than trying to compile and simulate
# -I points to the include directory where files such as `include wally-config.vh are found
# For more exhaustive (and sometimes spurious) warnings, add --Wall to the Verilator command
# Unfortunately, this produces a bunch of UNUSED and UNDRIVEN signal warnings in blocks that are configured to not exist.

140
src/wally/cvw.sv
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@ -28,9 +28,144 @@
// Instead, CORE-V-Wally loads the appropriate configuration one time and places it in a package
// that is referenced by all Wally modules but not by other subsystems.
// Load configuration-specific information
`include "wally-config.vh"
package cvw;
typedef struct packed {
logic [7:0] XLEN;
logic FPGA;
logic QEMU;
logic [63:0] AHBW;
logic [63:0] PA_BITS;
logic [31:0] MISA;
logic BUS_SUPPORTED;
logic ZICSR_SUPPORTED;
logic M_SUPPORTED;
logic ZMMUL_SUPPORTED;
logic F_SUPPORTED;
logic [7:0] PMP_ENTRIES;
logic [63:0] LLEN;
logic [63:0] FLEN;
logic [7:0] VPN_SEGMENT_BITS;
} cvw_t;
/*
// constants defining different privilege modes
// defined in Table 1.1 of the privileged spec
localparam M_MODE=(2'b11);
localparam S_MODE=(2'b01);
localparam U_MODE=(2'b00);
// Virtual Memory Constants
localparam VPN_SEGMENT_BITS = (P.XLEN == 32 ? 10 : 9)
`define VPN_BITS (`XLEN==32 ? (2*`VPN_SEGMENT_BITS) : (4*`VPN_SEGMENT_BITS))
`define PPN_BITS (`XLEN==32 ? 22 : 44)
`define PA_BITS (`XLEN==32 ? 34 : 56)
`define SVMODE_BITS (`XLEN==32 ? 1 : 4)
`define ASID_BASE (`XLEN==32 ? 22 : 44)
`define ASID_BITS (`XLEN==32 ? 9 : 16)
// constants to check SATP_MODE against
// defined in Table 4.3 of the privileged spec
`define NO_TRANSLATE 0
`define SV32 1
`define SV39 8
`define SV48 9
// macros to define supported modes
`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
`define B_SUPPORTED ((`ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED | `ZBS_SUPPORTED)) // not based on MISA
`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
`define E_SUPPORTED ((`MISA >> 4) % 2 == 1)
`define F_SUPPORTED ((`MISA >> 5) % 2 == 1)
`define I_SUPPORTED ((`MISA >> 8) % 2 == 1)
`define M_SUPPORTED ((`MISA >> 12) % 2 == 1)
`define Q_SUPPORTED ((`MISA >> 16) % 2 == 1)
`define S_SUPPORTED ((`MISA >> 18) % 2 == 1)
`define U_SUPPORTED ((`MISA >> 20) % 2 == 1)
// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
// logarithm of XLEN, used for number of index bits to select
`define LOG_XLEN (`XLEN == 32 ? 5 : 6)
// Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries)
`define PMPCFG_ENTRIES (`PMP_ENTRIES/8)
// Floating point constants for Quad, Double, Single, and Half precisions
`define Q_LEN 32'd128
`define Q_NE 32'd15
`define Q_NF 32'd112
`define Q_BIAS 32'd16383
`define Q_FMT 2'd3
`define D_LEN 32'd64
`define D_NE 32'd11
`define D_NF 32'd52
`define D_BIAS 32'd1023
`define D_FMT 2'd1
`define S_LEN 32'd32
`define S_NE 32'd8
`define S_NF 32'd23
`define S_BIAS 32'd127
`define S_FMT 2'd0
`define H_LEN 32'd16
`define H_NE 32'd5
`define H_NF 32'd10
`define H_BIAS 32'd15
`define H_FMT 2'd2
// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits
`define FLEN (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `S_LEN)
`define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `S_NE)
`define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `S_NF)
`define FMT (`Q_SUPPORTED ? 2'd3 : `D_SUPPORTED ? 2'd1 : 2'd0)
`define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `S_BIAS)
// Floating point constants needed for FPU paramerterization
`define FPSIZES ((32)'(`Q_SUPPORTED)+(32)'(`D_SUPPORTED)+(32)'(`F_SUPPORTED)+(32)'(`ZFH_SUPPORTED))
`define FMTBITS ((32)'(`FPSIZES>=3)+1)
`define LEN1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_LEN : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_LEN : `H_LEN)
`define NE1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NE : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NE : `H_NE)
`define NF1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NF : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NF : `H_NF)
`define FMT1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? 2'd1 : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? 2'd0 : 2'd2)
`define BIAS1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_BIAS : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_BIAS : `H_BIAS)
`define LEN2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_LEN : `H_LEN)
`define NE2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NE : `H_NE)
`define NF2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NF : `H_NF)
`define FMT2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? 2'd0 : 2'd2)
`define BIAS2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_BIAS : `H_BIAS)
// largest length in IEU/FPU
`define CVTLEN ((`NF<`XLEN) ? (`XLEN) : (`NF))
`define LLEN (($unsigned(`FLEN)<$unsigned(`XLEN)) ? ($unsigned(`XLEN)) : ($unsigned(`FLEN)))
`define LOGCVTLEN $unsigned($clog2(`CVTLEN+1))
`define NORMSHIFTSZ (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVb + 1 +`NF+1) > (3*`NF+6) ? (`DIVb + 1 +`NF+1) : (3*`NF+6)))
`define LOGNORMSHIFTSZ ($clog2(`NORMSHIFTSZ))
`define CORRSHIFTSZ (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVN+1+`NF) > (3*`NF+4) ? (`DIVN+1+`NF) : (3*`NF+4)))
// division constants
`define DIVN (((`NF<`XLEN) & `IDIV_ON_FPU) ? `XLEN : `NF+2) // standard length of input
`define LOGR ($clog2(`RADIX)) // r = log(R)
`define RK (`LOGR*`DIVCOPIES) // r*k used for intdiv preproc
`define LOGRK ($clog2(`RK)) // log2(r*k)
`define FPDUR ((`DIVN+1+(`LOGR*`DIVCOPIES))/(`LOGR*`DIVCOPIES)+(`RADIX/4))
`define DURLEN ($clog2(`FPDUR+1))
`define DIVb (`FPDUR*`LOGR*`DIVCOPIES-1) // canonical fdiv size (b)
`define DIVBLEN ($clog2(`DIVb+1)-1)
`define DIVa (`DIVb+1-`XLEN) // used for idiv on fpu
*/
// Disable spurious Verilator warnings
/* verilator lint_off STMTDLY */
/* verilator lint_off ASSIGNDLY */
/* verilator lint_off PINCONNECTEMPTY */
endpackage
/*
// Place configuration in a package
package cvw;
parameter XLEN = `XLEN;
@ -213,3 +348,4 @@ package cvw;
parameter DIVa = (`DIVb+1-`XLEN); // used for idiv on fpu
endpackage
*/

69
src/wally/wallypipelinedcore.sv
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@ -26,21 +26,20 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
//import cvw::*; // global CORE-V-Wally parameters
`include "wally-config.vh"
import cvw::*; // global CORE-V-Wally parameters
module wallypipelinedcore (
module wallypipelinedcore #(parameter cvw_t P) (
input logic clk, reset,
// Privileged
input logic MTimerInt, MExtInt, SExtInt, MSwInt,
input logic [63:0] MTIME_CLINT,
// Bus Interface
input logic [`AHBW-1:0] HRDATA,
input logic [P.AHBW-1:0] HRDATA,
input logic HREADY, HRESP,
output logic HCLK, HRESETn,
output logic [`PA_BITS-1:0] HADDR,
output logic [`AHBW-1:0] HWDATA,
output logic [`XLEN/8-1:0] HWSTRB,
output logic [P.PA_BITS-1:0] HADDR,
output logic [P.AHBW-1:0] HWDATA,
output logic [P.XLEN/8-1:0] HWSTRB,
output logic HWRITE,
output logic [2:0] HSIZE,
output logic [2:0] HBURST,
@ -58,15 +57,15 @@ module wallypipelinedcore (
logic IntDivE, W64E;
logic CSRReadM, CSRWriteM, PrivilegedM;
logic [1:0] AtomicM;
logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE;
logic [`XLEN-1:0] SrcAM;
logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE;
logic [P.XLEN-1:0] SrcAM;
logic [2:0] Funct3E;
logic [31:0] InstrD;
logic [31:0] InstrM, InstrOrigM;
logic [`XLEN-1:0] PCSpillF, PCE, PCLinkE;
logic [`XLEN-1:0] PCM;
logic [`XLEN-1:0] CSRReadValW, MDUResultW;
logic [`XLEN-1:0] UnalignedPCNextF, PC2NextF;
logic [P.XLEN-1:0] PCSpillF, PCE, PCLinkE;
logic [P.XLEN-1:0] PCM;
logic [P.XLEN-1:0] CSRReadValW, MDUResultW;
logic [P.XLEN-1:0] UnalignedPCNextF, PC2NextF;
logic [1:0] MemRWM;
logic InstrValidD, InstrValidE, InstrValidM;
logic InstrMisalignedFaultM;
@ -86,32 +85,32 @@ module wallypipelinedcore (
logic [4:0] RdE, RdM, RdW;
logic FPUStallD;
logic FWriteIntE;
logic [`FLEN-1:0] FWriteDataM;
logic [`XLEN-1:0] FIntResM;
logic [`XLEN-1:0] FCvtIntResW;
logic [P.FLEN-1:0] FWriteDataM;
logic [P.XLEN-1:0] FIntResM;
logic [P.XLEN-1:0] FCvtIntResW;
logic FCvtIntW;
logic FDivBusyE;
logic FRegWriteM;
logic FCvtIntStallD;
logic FpLoadStoreM;
logic [4:0] SetFflagsM;
logic [`XLEN-1:0] FIntDivResultW;
logic [P.XLEN-1:0] FIntDivResultW;
// memory management unit signals
logic ITLBWriteF;
logic ITLBMissF;
logic [`XLEN-1:0] SATP_REGW;
logic [P.XLEN-1:0] SATP_REGW;
logic STATUS_MXR, STATUS_SUM, STATUS_MPRV;
logic [1:0] STATUS_MPP, STATUS_FS;
logic [1:0] PrivilegeModeW;
logic [`XLEN-1:0] PTE;
logic [P.XLEN-1:0] PTE;
logic [1:0] PageType;
logic sfencevmaM, WFIStallM;
logic SelHPTW;
// PMA checker signals
var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0];
var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0];
var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0];
var logic [7:0] PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0];
// IMem stalls
logic IFUStallF;
@ -119,14 +118,14 @@ module wallypipelinedcore (
// cpu lsu interface
logic [2:0] Funct3M;
logic [`XLEN-1:0] IEUAdrE;
logic [`XLEN-1:0] WriteDataM;
logic [`XLEN-1:0] IEUAdrM;
logic [`LLEN-1:0] ReadDataW;
logic [P.XLEN-1:0] IEUAdrE;
logic [P.XLEN-1:0] WriteDataM;
logic [P.XLEN-1:0] IEUAdrM;
logic [P.LLEN-1:0] ReadDataW;
logic CommittedM;
// AHB ifu interface
logic [`PA_BITS-1:0] IFUHADDR;
logic [P.PA_BITS-1:0] IFUHADDR;
logic [2:0] IFUHBURST;
logic [1:0] IFUHTRANS;
logic [2:0] IFUHSIZE;
@ -134,9 +133,9 @@ module wallypipelinedcore (
logic IFUHREADY;
// AHB LSU interface
logic [`PA_BITS-1:0] LSUHADDR;
logic [`XLEN-1:0] LSUHWDATA;
logic [`XLEN/8-1:0] LSUHWSTRB;
logic [P.PA_BITS-1:0] LSUHADDR;
logic [P.XLEN-1:0] LSUHWDATA;
logic [P.XLEN/8-1:0] LSUHWSTRB;
logic LSUHWRITE;
logic LSUHREADY;
@ -203,7 +202,7 @@ module wallypipelinedcore (
.RdE, .RdM, .FIntResM, .FlushDCacheM,
.BranchD, .BranchE, .JumpD, .JumpE,
// Writeback stage
.CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[`XLEN-1:0]),
.CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[P.XLEN-1:0]),
.InstrValidM, .InstrValidE, .InstrValidD, .FCvtIntResW, .FCvtIntW,
// hazards
.StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
@ -243,7 +242,7 @@ module wallypipelinedcore (
.PCSpillF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW,
.LSUStallM);
if(`BUS_SUPPORTED) begin : ebu
if (P.BUS_SUPPORTED) begin : ebu
ebu ebu(// IFU connections
.clk, .reset,
// IFU interface
@ -281,7 +280,7 @@ module wallypipelinedcore (
.FlushD, .FlushE, .FlushM, .FlushW);
// privileged unit
if (`ZICSR_SUPPORTED) begin:priv
if (P.ZICSR_SUPPORTED) begin:priv
privileged priv(
.clk, .reset,
.FlushD, .FlushE, .FlushM, .FlushW, .StallD, .StallE, .StallM, .StallW,
@ -314,7 +313,7 @@ module wallypipelinedcore (
end
// multiply/divide unit
if (`M_SUPPORTED | `ZMMUL_SUPPORTED) begin:mdu
if (P.M_SUPPORTED | P.ZMMUL_SUPPORTED) begin:mdu
mdu mdu(.clk, .reset, .StallM, .StallW, .FlushE, .FlushM, .FlushW,
.ForwardedSrcAE, .ForwardedSrcBE,
.Funct3E, .Funct3M, .IntDivE, .W64E,
@ -325,12 +324,12 @@ module wallypipelinedcore (
end
// floating point unit
if (`F_SUPPORTED) begin:fpu
if (P.F_SUPPORTED) begin:fpu
fpu fpu(
.clk, .reset,
.FRM_REGW, // Rounding mode from CSR
.InstrD, // instruction from IFU
.ReadDataW(ReadDataW[`FLEN-1:0]),// Read data from memory
.ReadDataW(ReadDataW[P.FLEN-1:0]),// Read data from memory
.ForwardedSrcAE, // Integer input being processed (from IEU)
.StallE, .StallM, .StallW, // stall signals from HZU
.FlushE, .FlushM, .FlushW, // flush signals from HZU

19
src/wally/wallypipelinedsoc.sv
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@ -26,22 +26,21 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
//import cvw::*; // global CORE-V-Wally parameters
`include "wally-config.vh"
import cvw::*; // global CORE-V-Wally parameters
module wallypipelinedsoc (
module wallypipelinedsoc #(parameter cvw_t P) (
input logic clk,
input logic reset_ext, // external asynchronous reset pin
output logic reset, // reset synchronized to clk to prevent races on release
// AHB Interface
input logic [`AHBW-1:0] HRDATAEXT,
input logic [P.AHBW-1:0] HRDATAEXT,
input logic HREADYEXT, HRESPEXT,
output logic HSELEXT,
// outputs to external memory, shared with uncore memory
output logic HCLK, HRESETn,
output logic [`PA_BITS-1:0] HADDR,
output logic [`AHBW-1:0] HWDATA,
output logic [`XLEN/8-1:0] HWSTRB,
output logic [P.PA_BITS-1:0] HADDR,
output logic [P.AHBW-1:0] HWDATA,
output logic [P.XLEN/8-1:0] HWSTRB,
output logic HWRITE,
output logic [2:0] HSIZE,
output logic [2:0] HBURST,
@ -64,7 +63,7 @@ module wallypipelinedsoc (
);
// Uncore signals
logic [`AHBW-1:0] HRDATA; // from AHB mux in uncore
logic [P.AHBW-1:0] HRDATA; // from AHB mux in uncore
logic HRESP; // response from AHB
logic MTimerInt, MSwInt; // timer and software interrupts from CLINT
logic [63:0] MTIME_CLINT; // from CLINT to CSRs
@ -74,14 +73,14 @@ module wallypipelinedsoc (
synchronizer resetsync(.clk, .d(reset_ext), .q(reset));
// instantiate processor and internal memories
wallypipelinedcore core(.clk, .reset,
wallypipelinedcore #(P) core (.clk, .reset,
.MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT,
.HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB,
.HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK
);
// instantiate uncore if a bus interface exists
if (`BUS_SUPPORTED) begin : uncore
if (P.BUS_SUPPORTED) begin : uncore
uncore uncore(.HCLK, .HRESETn, .TIMECLK,
.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
.HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT,

69
src/wally/wallypipelinedsoc_32e.sv Normal file
View File

@ -0,0 +1,69 @@
///////////////////////////////////////////
// wally-pipelinedsoc.sv
//
// Written: David_Harris@hmc.edu 6 November 2020
// Modified:
//
// Purpose: System on chip including pipelined processor and uncore memories/peripherals
//
// Documentation: RISC-V System on Chip Design (Figure 6.20)
//
// A component of the CORE-V-WALLY configurable RISC-V project.
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
import cvw::*; // global CORE-V-Wally parameters
`include "rv32e-config.vh"
module wallypipelinedsoc_32e (
input logic clk,
input logic reset_ext, // external asynchronous reset pin
output logic reset, // reset synchronized to clk to prevent races on release
// AHB Interface
input logic [AHBW-1:0] HRDATAEXT,
input logic HREADYEXT, HRESPEXT,
output logic HSELEXT,
// outputs to external memory, shared with uncore memory
output logic HCLK, HRESETn,
output logic [PA_BITS-1:0] HADDR,
output logic [AHBW-1:0] HWDATA,
output logic [XLEN/8-1:0] HWSTRB,
output logic HWRITE,
output logic [2:0] HSIZE,
output logic [2:0] HBURST,
output logic [3:0] HPROT,
output logic [1:0] HTRANS,
output logic HMASTLOCK,
output logic HREADY,
// I/O Interface
input logic TIMECLK, // optional for CLINT MTIME counter
input logic [31:0] GPIOPinsIn, // inputs from GPIO
output logic [31:0] GPIOPinsOut, // output values for GPIO
output logic [31:0] GPIOPinsEn, // output enables for GPIO
input logic UARTSin, // UART serial data input
output logic UARTSout, // UART serial data output
input logic SDCCmdIn, // SDC Command input
output logic SDCCmdOut, // SDC Command output
output logic SDCCmdOE, // SDC Command output enable
input logic [3:0] SDCDatIn, // SDC data input
output logic SDCCLK // SDC clock
);
`include "parameter-defs.vh"
wallypipelinedsoc #(P) soc(.*);
endmodule

96
testbench/testbench.sv
View File

@ -71,8 +71,8 @@ logic [3:0] dummy;
logic riscofTest;
logic StartSample, EndSample;
flopenr #(`XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW);
flopenr #(32) InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.InstrM, InstrW);
flopenr #(`XLEN) PCWReg(clk, reset, ~dut.soc.core.ieu.dp.StallW, dut.soc.core.ifu.PCM, PCW);
flopenr #(32) InstrWReg(clk, reset, ~dut.soc.core.ieu.dp.StallW, dut.soc.core.ifu.InstrM, InstrW);
// check assertions for a legal configuration
riscvassertions riscvassertions();
@ -197,16 +197,16 @@ logic [3:0] dummy;
assign SDCDat = '0;
end
wallypipelinedsoc dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
wallypipelinedsoc_32e dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
.HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
.UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK);
// Track names of instructions
instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE,
dut.core.ifu.InstrRawF[31:0],
dut.core.ifu.InstrD, dut.core.ifu.InstrE,
dut.core.ifu.InstrM, InstrW,
instrTrackerTB it(clk, reset, dut.soc.core.ieu.dp.FlushE,
dut.soc.core.ifu.InstrRawF[31:0],
dut.soc.core.ifu.InstrD, dut.soc.core.ifu.InstrE,
dut.soc.core.ifu.InstrM, InstrW,
InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
// initialize tests
@ -232,7 +232,7 @@ logic [3:0] dummy;
// the design.
if (TEST == "coremark")
for (i=MemStartAddr; i<MemEndAddr; i = i+1)
dut.uncore.uncore.ram.ram.memory.RAM[i] = 64'h0;
dut.soc.uncore.uncore.ram.ram.memory.RAM[i] = 64'h0;
// read test vectors into memory
pathname = tvpaths[tests[0].atoi()];
@ -245,14 +245,14 @@ logic [3:0] dummy;
string romfilename, sdcfilename;
romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
sdcfilename = {"../testbench/sdc/ramdisk2.hex"};
$readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
$readmemh(romfilename, dut.soc.uncore.uncore.bootrom.bootrom.memory.ROM);
$readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
// force sdc timers
force dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
force dut.soc.uncore.uncore.sdc.SDC.LimitTimers = 1;
end else begin
if (`IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
else if (`BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
if (`DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
if (`IROM_SUPPORTED) $readmemh(memfilename, dut.soc.core.ifu.irom.irom.rom.ROM);
else if (`BUS_SUPPORTED) $readmemh(memfilename, dut.soc.uncore.uncore.ram.ram.memory.RAM);
if (`DTIM_SUPPORTED) $readmemh(memfilename, dut.soc.core.lsu.dtim.dtim.ram.RAM);
end
if (riscofTest) begin
@ -292,7 +292,7 @@ logic [3:0] dummy;
end
end else begin
if (TEST == "coremark")
if (dut.core.priv.priv.EcallFaultM) begin
if (dut.soc.core.priv.priv.EcallFaultM) begin
$display("Benchmark: coremark is done.");
$stop;
end
@ -356,8 +356,8 @@ logic [3:0] dummy;
/* verilator lint_off INFINITELOOP */
while (signature[i] !== 'bx) begin
logic [`XLEN-1:0] sig;
if (`DTIM_SUPPORTED) sig = dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i];
else if (`UNCORE_RAM_SUPPORTED) sig = dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
if (`DTIM_SUPPORTED) sig = dut.soc.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i];
else if (`UNCORE_RAM_SUPPORTED) sig = dut.soc.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
//$display("signature[%h] = %h sig = %h", i, signature[i], sig);
if (signature[i] !== sig & (signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin
errors = errors+1;
@ -389,10 +389,10 @@ logic [3:0] dummy;
//pathname = tvpaths[tests[0]];
if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
else memfilename = {pathname, tests[test], ".elf.memfile"};
//$readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
if (`IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
else if (`UNCORE_RAM_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
if (`DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
//$readmemh(memfilename, dut.soc.uncore.uncore.ram.ram.memory.RAM);
if (`IROM_SUPPORTED) $readmemh(memfilename, dut.soc.core.ifu.irom.irom.rom.ROM);
else if (`UNCORE_RAM_SUPPORTED) $readmemh(memfilename, dut.soc.uncore.uncore.ram.ram.memory.RAM);
if (`DTIM_SUPPORTED) $readmemh(memfilename, dut.soc.core.lsu.dtim.dtim.ram.RAM);
if (riscofTest) begin
ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"};
@ -481,13 +481,13 @@ logic [3:0] dummy;
always @(negedge clk) begin
if(StartSample) begin
for(HPMCindex = 0; HPMCindex < 32; HPMCindex += 1) begin
InitialHPMCOUNTERH[HPMCindex] <= dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex];
InitialHPMCOUNTERH[HPMCindex] <= dut.soc.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex];
end
end
if(EndSample) begin
for(HPMCindex = 0; HPMCindex < HPMCnames.size(); HPMCindex += 1) begin
// unlikely to have more than 10M in any counter.
$display("Cnt[%2d] = %7d %s", HPMCindex, dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex] - InitialHPMCOUNTERH[HPMCindex], HPMCnames[HPMCindex]);
$display("Cnt[%2d] = %7d %s", HPMCindex, dut.soc.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex] - InitialHPMCOUNTERH[HPMCindex], HPMCnames[HPMCindex]);
end
end
end
@ -509,15 +509,15 @@ logic [3:0] dummy;
// or sd gp, -56(t0)
// or on a jump to self infinite loop (6f) for RISC-V Arch tests
logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls
if (`ZICSR_SUPPORTED) assign ecf = dut.core.priv.priv.EcallFaultM;
if (`ZICSR_SUPPORTED) assign ecf = dut.soc.core.priv.priv.EcallFaultM;
else assign ecf = 0;
assign DCacheFlushStart = ecf &
(dut.core.ieu.dp.regf.rf[3] == 1 |
(dut.core.ieu.dp.regf.we3 &
dut.core.ieu.dp.regf.a3 == 3 &
dut.core.ieu.dp.regf.wd3 == 1)) |
((dut.core.ifu.InstrM == 32'h6f | dut.core.ifu.InstrM == 32'hfc32a423 | dut.core.ifu.InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM ) |
((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" );
(dut.soc.core.ieu.dp.regf.rf[3] == 1 |
(dut.soc.core.ieu.dp.regf.we3 &
dut.soc.core.ieu.dp.regf.a3 == 3 &
dut.soc.core.ieu.dp.regf.wd3 == 1)) |
((dut.soc.core.ifu.InstrM == 32'h6f | dut.soc.core.ifu.InstrM == 32'hfc32a423 | dut.soc.core.ifu.InstrM == 32'hfc32a823) & dut.soc.core.ieu.c.InstrValidM ) |
((dut.soc.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" );
DCacheFlushFSM DCacheFlushFSM(.clk(clk),
.reset(reset),
@ -532,17 +532,17 @@ logic [3:0] dummy;
always @(*) begin
if(reset) begin
for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin
force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
force dut.soc.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
end
for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin
force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
force dut.soc.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
end
#1;
for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin
release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex];
release dut.soc.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex];
end
for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin
release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex];
release dut.soc.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex];
end
end
end
@ -556,7 +556,7 @@ logic [3:0] dummy;
logic PCSrcM;
string LogFile;
logic resetD, resetEdge;
flopenrc #(1) PCSrcMReg(clk, reset, dut.core.FlushM, ~dut.core.StallM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM);
flopenrc #(1) PCSrcMReg(clk, reset, dut.soc.core.FlushM, ~dut.soc.core.StallM, dut.soc.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM);
flop #(1) ResetDReg(clk, reset, resetD);
assign resetEdge = ~reset & resetD;
initial begin
@ -566,9 +566,9 @@ logic [3:0] dummy;
always @(posedge clk) begin
if(resetEdge) $fwrite(file, "TRAIN\n");
if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename);
if(dut.core.ifu.InstrClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
if(dut.soc.core.ifu.InstrClassM[0] & ~dut.soc.core.StallW & ~dut.soc.core.FlushW & dut.soc.core.InstrValidM) begin
direction = PCSrcM ? "t" : "n";
$fwrite(file, "%h %s\n", dut.core.PCM, direction);
$fwrite(file, "%h %s\n", dut.soc.core.PCM, direction);
end
if(EndSample) $fwrite(file, "END %s\n", memfilename);
end
@ -610,12 +610,12 @@ module DCacheFlushFSM
logic [`XLEN-1:0] ShadowRAM[`UNCORE_RAM_BASE>>(1+`XLEN/32):(`UNCORE_RAM_RANGE+`UNCORE_RAM_BASE)>>1+(`XLEN/32)];
if(`DCACHE_SUPPORTED) begin
localparam numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES;
localparam numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS;
localparam linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN;
localparam linelen = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN;
localparam sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN;
localparam cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM;
localparam numlines = testbench.dut.soc.core.lsu.bus.dcache.dcache.NUMLINES;
localparam numways = testbench.dut.soc.core.lsu.bus.dcache.dcache.NUMWAYS;
localparam linebytelen = testbench.dut.soc.core.lsu.bus.dcache.dcache.LINEBYTELEN;
localparam linelen = testbench.dut.soc.core.lsu.bus.dcache.dcache.LINELEN;
localparam sramlen = testbench.dut.soc.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN;
localparam cachesramwords = testbench.dut.soc.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM;
localparam numwords = sramlen/`XLEN;
localparam lognumlines = $clog2(numlines);
localparam loglinebytelen = $clog2(linebytelen);
@ -638,13 +638,13 @@ module DCacheFlushFSM
.loglinebytelen(loglinebytelen), .sramlen(sramlen))
copyShadow(.clk,
.start,
.tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][`PA_BITS-1-tagstart:0]),
.valid(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].ValidBits[index]),
.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].DirtyBits[index]),
.tag(testbench.dut.soc.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][`PA_BITS-1-tagstart:0]),
.valid(testbench.dut.soc.core.lsu.bus.dcache.dcache.CacheWays[way].ValidBits[index]),
.dirty(testbench.dut.soc.core.lsu.bus.dcache.dcache.CacheWays[way].DirtyBits[index]),
// these dirty bit selections would be needed if dirty is moved inside the tag array.
//.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].dirty.DirtyMem.RAM[index]),
//.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][`PA_BITS+tagstart]),
.data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].CacheDataMem.RAM[index]),
//.dirty(testbench.dut.soc.core.lsu.bus.dcache.dcache.CacheWays[way].dirty.DirtyMem.RAM[index]),
//.dirty(testbench.dut.soc.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][`PA_BITS+tagstart]),
.data(testbench.dut.soc.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].CacheDataMem.RAM[index]),
.index(index),
.cacheWord(cacheWord),
.CacheData(CacheData[way][index][cacheWord]),