Ross Thompson a4907b5d29 Lee Moore found another bug using imperas. ... An ITLB miss concurrent with a d cache flush did not interlock. The LSU should suppress the d cache flush until the hptw fills the missing tlb entry.		2023-02-02 23:52:21 -06:00
..
slack-notifier
wave-dos
buildrootBugFinder.py
fpga-wave.do	Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage.	2022-12-23 15:10:37 -06:00
imperas.ic	add im flags for compressed disass	2023-01-18 13:37:28 +00:00
lint-wally	Converted rv32ic to rv32imc	2023-01-29 11:33:54 -08:00
linux-wave.do	Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage.	2022-12-23 15:10:37 -06:00
make-tests.sh
Makefile	Makefile and setup cleanup	2023-01-15 20:27:12 -08:00
makefile-memfile	Clean up warnings from Questa	2023-01-17 13:43:39 -08:00
regression-wally	Converted rv32ic to rv32imc	2023-01-29 11:33:54 -08:00
run-imperasdv-tests.bash	update	2023-01-19 13:29:46 +00:00
sim-buildroot
sim-buildroot-batch
sim-imperas	Created scripts to install imperas and run a single test using imperas.	2023-01-31 13:51:05 -06:00
sim-testfloat
sim-testfloat-batch
sim-wally
sim-wally-batch
test	test	2023-01-20 15:23:38 -08:00
testfloat.do
wally-pipelined-batch.do	Converted rv32ic to rv32imc	2023-01-29 11:33:54 -08:00
wally-pipelined-imperas-no-idv.do	refer to correct path	2023-01-18 13:26:07 +00:00
wally-pipelined-imperas.do	Somehow the imperas files spilled into the main branch.	2023-01-17 15:39:34 -06:00
wally-pipelined.do	Updated tests for fpga and BP.	2022-12-18 16:24:26 -06:00
wave-all.do	Changing signal name to ImmExtD/E to match figures	2023-01-17 06:33:58 -08:00
wave-fpu.do	reworked negitive sticky bit handeling in fma	2022-12-23 17:01:34 -06:00
wave.do	Lee Moore found another bug using imperas.	2023-02-02 23:52:21 -06:00