cvw/pipelined
Ross Thompson c4a9354c13 Replaced PCLinkX registers with a +2/4 adder in the execution stage.
David and I estimate this is lower hardware cost.
2023-02-03 18:19:47 -06:00
..
config Fixed merge conflict to get synthesis working again 2023-02-01 04:43:57 -08:00
regression Lee Moore found another bug using imperas. 2023-02-02 23:52:21 -06:00
src Replaced PCLinkX registers with a +2/4 adder in the execution stage. 2023-02-03 18:19:47 -06:00
testbench Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-01-31 14:40:19 -08:00