forked from Github_Repos/cvw
47 lines
1.8 KiB
Markdown
47 lines
1.8 KiB
Markdown
The FPGA currently only targets the VCU118 board.
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* Build Process
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cd generator
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make
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* Description
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The generator makefile creates 4 IP blocks; proc_sys_reset, ddr4,
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axi_clock_converter, and ahblite_axi_bridge. Then it reads in the 4 IP blocks
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and builds wally. fpga/src/fpgaTop.v is the top level which instanciates
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wallypipelinedsoc.sv and the 4 IP blocks. The FPGA include and ILA (In logic
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analyzer) which provides the current instruction PCM, instrM, etc along with
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a large number of debuging signals.
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* Programming the flash card
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You'll need to write the linux image to the flash card. Use the convert2bin.py
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script in pipelined/linux-testgen/linux-testvectors/ to convert the ram.txt
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file from QEMU's preload to generate the binary. Then to copy
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sudo dd if=ram.bin of=<path to flash card>.
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* Loading the FPGA
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After the build process is complete about 2 hrs on an i9-7900x. Launch vivado's
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gui and open the WallyFPGA.xpr project file. Open the hardware manager under
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program and debug. Open target and then program with the bit file.
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* Test Run
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Once the FPGA is programed the 3 MSB LEDs in the upper right corner provide
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status of the reset and ddr4 calibration. LED 7 should always be lit.
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LED 6 will light if the DDR4 is not calibrated. LED 6 will be lit once
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wally begins running.
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Next the bootloader program will copy the flash card into the DDR4 memory.
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When this done the lower 5 LEDs will blink 5 times and then try to boot
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the program loaded in the DDR4 memory at physical address 0x8000_0000.
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* Connecting uart
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You'll need to connect both usb cables. The first connects the FPGA programer
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while the connect connects UART. UART is configured to use 57600 baud with
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no parity, 8 data bits, and 1 stop bit. sudo screen /dev/ttyUSB1 57600 should
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let you view the com port.
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