forked from Github_Repos/cvw
217 lines
10 KiB
Systemverilog
217 lines
10 KiB
Systemverilog
///////////////////////////////////////////
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// cache (data cache)
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//
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// Written: ross1728@gmail.com July 07, 2021
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// Implements the L1 data cache
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//
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// Purpose: Storage for data and meta data.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
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input logic clk,
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input logic reset,
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// cpu side
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input logic CPUBusy,
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input logic [1:0] RW,
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input logic [1:0] Atomic,
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input logic FlushCache,
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input logic InvalidateCacheM,
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input logic [11:0] NextAdr, // virtual address, but we only use the lower 12 bits.
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input logic [`PA_BITS-1:0] PAdr, // physical address
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input logic [`XLEN-1:0] FinalWriteData,
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output logic CacheCommitted,
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output logic CacheStall,
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// to performance counters to cpu
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output logic CacheMiss,
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output logic CacheAccess,
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output logic save, restore,
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// lsu control
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input logic IgnoreRequest,
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// Bus fsm interface
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output logic CacheFetchLine,
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output logic CacheWriteLine,
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input logic CacheBusAck,
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output logic [`PA_BITS-1:0] CacheBusAdr,
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input logic [LINELEN-1:0] CacheMemWriteData,
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output logic [LINELEN-1:0] ReadDataLine);
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// Cache parameters
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localparam LINEBYTELEN = LINELEN/8;
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localparam OFFSETLEN = $clog2(LINEBYTELEN);
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localparam SETLEN = $clog2(NUMLINES);
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localparam SETTOP = SETLEN+OFFSETLEN;
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localparam TAGLEN = `PA_BITS - SETTOP;
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localparam WORDSPERLINE = LINELEN/`XLEN;
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localparam LOGWPL = $clog2(WORDSPERLINE);
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localparam LOGXLENBYTES = $clog2(`XLEN/8);
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localparam FlushAdrThreshold = NUMLINES - 1;
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logic [1:0] SelAdr;
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logic [SETLEN-1:0] RAdr;
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logic [LINELEN-1:0] SRAMWriteData;
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logic SetValid, ClearValid;
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logic SetDirty, ClearDirty;
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logic [LINELEN-1:0] ReadDataLineWay [NUMWAYS-1:0];
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logic [NUMWAYS-1:0] WayHit;
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logic CacheHit;
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logic [WORDSPERLINE-1:0] SRAMWordEnable;
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logic SRAMWordWriteEnable;
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logic SRAMLineWriteEnable;
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logic [NUMWAYS-1:0] SRAMLineWayWriteEnable;
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logic [NUMWAYS-1:0] SRAMWayWriteEnable;
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logic [NUMWAYS-1:0] SRAMWordWayWriteEnable;
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logic [NUMWAYS-1:0] VictimWay;
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logic [NUMWAYS-1:0] VictimDirtyWay;
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logic VictimDirty;
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logic [2**LOGWPL-1:0] MemPAdrDecoded;
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logic [TAGLEN-1:0] VictimTagWay [NUMWAYS-1:0];
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logic [TAGLEN-1:0] VictimTag;
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logic [SETLEN-1:0] FlushAdr;
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logic [SETLEN-1:0] FlushAdrP1;
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logic FlushAdrCntEn;
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logic FlushAdrCntRst;
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logic FlushAdrFlag;
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logic FlushWayFlag;
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logic [NUMWAYS-1:0] FlushWay;
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logic [NUMWAYS-1:0] NextFlushWay;
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logic FlushWayCntEn;
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logic FlushWayCntRst;
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logic SelEvict;
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logic LRUWriteEn;
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logic SelFlush;
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logic ResetOrFlushAdr, ResetOrFlushWay;
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logic [NUMWAYS-1:0] WayHitSaved, WayHitRaw;
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logic [LINELEN-1:0] ReadDataLineRaw, ReadDataLineSaved;
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logic [NUMWAYS-1:0] SelectedWay;
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logic [NUMWAYS-1:0] SetValidWay, ClearValidWay, SetDirtyWay, ClearDirtyWay;
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Read Path
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Choose read address (RAdr). Normally use NextAdr, but use PAdr during stalls
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// and FlushAdr when handling D$ flushes
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mux3 #(SETLEN) AdrSelMux(
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.d0(NextAdr[SETTOP-1:OFFSETLEN]), .d1(PAdr[SETTOP-1:OFFSETLEN]), .d2(FlushAdr),
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.s(SelAdr), .y(RAdr));
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// Array of cache ways, along with victim, hit, dirty, and read merging logic
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cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN) CacheWays[NUMWAYS-1:0](
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.clk, .reset, .RAdr, .PAdr,
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.SRAMWayWriteEnable,
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.SRAMWordEnable,
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.TagWriteEnable(SRAMLineWayWriteEnable),
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.WriteData(SRAMWriteData),
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.SetValid(SetValidWay), .ClearValid(ClearValidWay), .SetDirty(SetDirtyWay), .ClearDirty(ClearDirtyWay),
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.SelEvict, .Victim(VictimWay), .Flush(FlushWay),
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.SelFlush,
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.SelectedReadDataLine(ReadDataLineWay), .WayHit(WayHitRaw), .VictimDirty(VictimDirtyWay), .VictimTag(VictimTagWay),
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.InvalidateAll(InvalidateCacheM));
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if(NUMWAYS > 1) begin:vict
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cachereplacementpolicy #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cachereplacementpolicy(
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.clk, .reset, .WayHit, .VictimWay, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .RAdr, .LRUWriteEn);
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end else assign VictimWay = 1'b1; // one hot.
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assign CacheHit = | WayHit;
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assign VictimDirty = | VictimDirtyWay;
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// ReadDataLineWay is a 2d array of cache line len by number of ways.
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// Need to OR together each way in a bitwise manner.
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// Final part of the AO Mux. First is the AND in the cacheway.
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or_rows #(NUMWAYS, LINELEN) ReadDataAOMux(.a(ReadDataLineWay), .y(ReadDataLine));
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or_rows #(NUMWAYS, TAGLEN) VictimTagAOMux(.a(VictimTagWay), .y(VictimTag));
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// Because of the sram clocked read when the ieu is stalled the read data maybe lost.
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// There are two ways to resolve. 1. We can replay the read of the sram or we can save
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// the data. Replay is eaiser but creates a longer critical path.
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// save/restore only wayhit and readdata.
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if(!`REPLAY) begin
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flopenr #(NUMWAYS) wayhitsavereg(clk, save, reset, WayHitRaw, WayHitSaved);
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mux2 #(NUMWAYS) saverestoremux(WayHitRaw, WayHitSaved, restore, WayHit);
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end else assign WayHit = WayHitRaw;
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Write Path: Write Enables
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/////////////////////////////////////////////////////////////////////////////////////////////
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// *** Ross considering restructuring
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// move decoder and wordwritenable into cacheway.
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onehotdecoder #(LOGWPL) adrdec(
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.bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecoded));
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assign SRAMWordEnable = SRAMLineWriteEnable ? '1 : MemPAdrDecoded; // OR
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assign SRAMLineWayWriteEnable = SRAMLineWriteEnable ? VictimWay : '0; // AND
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assign SRAMWordWayWriteEnable = SRAMWordWriteEnable ? WayHit : '0; // AND
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mux2 #(NUMWAYS) WriteEnableMux(.d0(SRAMWordWayWriteEnable), .d1(VictimWay),
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.s(SRAMLineWriteEnable), .y(SRAMWayWriteEnable));
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mux2 #(LINELEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteData}}),
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.d1(CacheMemWriteData), .s(SRAMLineWriteEnable), .y(SRAMWriteData));
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mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
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.d1({VictimTag, PAdr[SETTOP-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
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.d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}),
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.s({SelFlush, SelEvict}),
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.y(CacheBusAdr));
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Flush address and way generation during flush
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/////////////////////////////////////////////////////////////////////////////////////////////
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assign ResetOrFlushAdr = reset | FlushAdrCntRst;
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flopenr #(SETLEN) FlushAdrReg(.clk, .reset(ResetOrFlushAdr),
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.en(FlushAdrCntEn), .d(FlushAdrP1), .q(FlushAdr));
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assign FlushAdrP1 = FlushAdr + 1'b1;
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assign FlushAdrFlag = (FlushAdr == FlushAdrThreshold[SETLEN-1:0]);
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assign ResetOrFlushWay = reset | FlushWayCntRst;
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flopenl #(NUMWAYS) FlushWayReg(.clk, .load(ResetOrFlushWay),
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.en(FlushWayCntEn), .val({{NUMWAYS-1{1'b0}}, 1'b1}),
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.d(NextFlushWay), .q(FlushWay));
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assign FlushWayFlag = FlushWay[NUMWAYS-1];
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assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]};
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assign SelectedWay = SelFlush ? FlushWay : (SRAMLineWriteEnable ? VictimWay : WayHit);
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assign SetValidWay = SetValid ? SelectedWay : '0;
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assign ClearValidWay = ClearValid ? SelectedWay : '0;
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assign SetDirtyWay = SetDirty ? SelectedWay : '0;
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assign ClearDirtyWay = ClearDirty ? SelectedWay : '0;
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Cache FSM
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/////////////////////////////////////////////////////////////////////////////////////////////
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cachefsm cachefsm(.clk, .reset, .CacheFetchLine, .CacheWriteLine, .CacheBusAck,
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.RW, .Atomic, .CPUBusy, .IgnoreRequest,
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.CacheHit, .VictimDirty, .CacheStall, .CacheCommitted,
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.CacheMiss, .CacheAccess, .SelAdr, .SetValid,
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.ClearValid, .SetDirty, .ClearDirty, .SRAMWordWriteEnable,
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.SRAMLineWriteEnable, .SelEvict, .SelFlush,
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.FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst,
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.FlushWayCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache,
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.save, .restore,
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.LRUWriteEn);
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endmodule
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