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wave-dos
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working GPIO interrupt demo
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2021-04-15 21:09:15 -04:00 |
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regression-wally.py
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regression: use busybear batch instead
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2021-03-25 15:34:10 -04:00 |
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run_sim.sh
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-03-30 15:25:07 -04:00 |
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sim-buildroot
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start to add buildroot testbench
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2021-04-16 23:27:29 -04:00 |
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sim-buildroot-batch
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start to add buildroot testbench
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2021-04-16 23:27:29 -04:00 |
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sim-busybear
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busybear: add sim-busybear and sim-busybear-batch based on sim-wally
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2021-03-01 21:01:15 +00:00 |
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sim-busybear-batch
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busybear: make a second .do file with better optimization for command line mode
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2021-03-08 19:35:00 +00:00 |
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sim-peripherals
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Yee hoo first draft of PLIC plus self-checking tests
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2021-04-04 06:40:53 -04:00 |
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sim-wally
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Added test configurations
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2021-01-25 11:28:43 -05:00 |
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sim-wally-batch
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Fixed issue with sim-wally-batch. Are people still using this script?
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2021-03-17 11:17:52 -05:00 |
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sim-wally-batch-muldiv
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-03-30 15:25:07 -04:00 |
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sim-wally-batch-rv32ic
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fixed sim-wally-32ic
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2021-04-08 13:40:16 -04:00 |
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sim-wally-rv32ic
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fixed sim-wally-32ic
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2021-04-08 13:40:16 -04:00 |
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vish_stacktrace.vstf
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Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.
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2021-04-02 06:27:37 -05:00 |
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wally-buildroot-batch.do
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start to add buildroot testbench
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2021-04-16 23:27:29 -04:00 |
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wally-buildroot.do
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buildroot: sim is now running!
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2021-04-17 14:44:32 -04:00 |
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wally-busybear-batch.do
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busybear: clean up questa warnings
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2021-03-31 14:02:15 -04:00 |
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wally-busybear.do
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busybear: clean up questa warnings
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2021-03-31 14:02:15 -04:00 |
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wally-coremark_bare.do
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-03-30 15:25:07 -04:00 |
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wally-coremark.do
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-03-30 15:25:07 -04:00 |
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wally-pipelined-batch-muldiv.do
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-03-30 15:25:07 -04:00 |
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wally-pipelined-batch.do
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Condense the parallel and non-parallel wally-pipelined-batch.do files into one
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2021-03-16 18:15:13 -04:00 |
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wally-pipelined-muldiv.do
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Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.
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2021-04-02 06:27:37 -05:00 |
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wally-pipelined-ross.do
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Converted branch predictor preloads to use system verilog rather than modelsim's load command.
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2021-03-15 12:39:44 -05:00 |
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wally-pipelined.do
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merge testbench
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2021-04-08 14:28:01 -04:00 |
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wally-privileged.do
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Fix bugs with privileged tests
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2021-03-25 14:06:05 -04:00 |
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wave-all.do
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-03-30 15:25:07 -04:00 |
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wave.do
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Partial fix to the integer divide stall issue.
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2021-04-02 15:32:15 -05:00 |
