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slack-notifier
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added instructions to slack notifier
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2022-05-18 16:50:31 -07:00 |
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wave-dos
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Added generate around uncore.
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2022-08-25 10:35:24 -05:00 |
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buildrootBugFinder.py
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update to match new filesystem organization
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2022-03-26 21:28:32 +00:00 |
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fpga-wave.do
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Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage.
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2022-12-23 15:10:37 -06:00 |
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imperas.ic
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add im flags for compressed disass
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2023-01-18 13:37:28 +00:00 |
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lint-wally
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Clean up unused FPU signals
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2022-12-22 23:53:09 -08:00 |
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linux-wave.do
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Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage.
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2022-12-23 15:10:37 -06:00 |
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make-tests.sh
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simplified make-tests.sh to run the current makefile in regression
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2022-05-17 17:29:34 -07:00 |
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Makefile
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More riscof makefile tuning
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2022-07-25 21:15:56 +00:00 |
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makefile-memfile
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plic-s debug
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2022-08-03 12:33:09 +00:00 |
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regression-wally
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Moved floating-point tests earlier in Wally config
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2022-12-25 22:31:20 -08:00 |
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run-imperasdv-tests.bash
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update
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2023-01-19 13:29:46 +00:00 |
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sim-buildroot
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switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv
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2022-03-01 03:11:43 +00:00 |
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sim-buildroot-batch
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sim-buildroot-batch now runs wally-pipelined-batch
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2022-07-06 18:06:43 -07:00 |
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sim-testfloat
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Running 16-bit square root cases first in testfloat
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2022-09-07 11:11:35 -07:00 |
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sim-testfloat-batch
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fixed error in divsqrt
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2022-07-14 18:16:00 +00:00 |
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sim-wally
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FPU test list
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2022-12-01 10:18:36 -08:00 |
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sim-wally-batch
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Renamed endianswap to match module name
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2022-10-04 17:33:49 +00:00 |
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testfloat.do
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Moved fpu modules into subdirectories
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2022-09-20 04:12:05 -07:00 |
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wally-harvard.do
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Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.
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2022-01-13 22:21:43 -06:00 |
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wally-pipelined-batch.do
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Reverted the IROM/DTIM address range modelsim assignment.
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2022-11-30 17:13:33 -06:00 |
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wally-pipelined-imperas-no-idv.do
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refer to correct path
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2023-01-18 13:26:07 +00:00 |
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wally-pipelined-imperas.do
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Code refactor and addition of rvvi interface
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2023-01-17 12:47:38 +00:00 |
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wally-pipelined.do
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Updated tests for fpga and BP.
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2022-12-18 16:24:26 -06:00 |
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wave-all.do
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Renamed signals in the cache.
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2022-11-29 10:52:40 -06:00 |
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wave-fpu.do
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reworked negitive sticky bit handeling in fma
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2022-12-23 17:01:34 -06:00 |
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wave.do
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Partial fix for misaligned LD/ST
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2023-01-18 17:11:39 +00:00 |
