forked from Github_Repos/cvw
69f6b291c6
I found the problem. We use a Committed(F/M) signal to indicate the IFU or LSU has an ongoing cache or bus transaction and should not be interrupted. At the time of the mret, the IFU is fetching uncacheable invalid instructions asserting CommittedF. As the IFU finishes the request it unstalls the pipeline but continues to assert CommittedF. (This is not necessary for the IFU). In the same cycle the LSU d cache misses. Because CommittedF is blocking the interrupt the d cache submits a cache line fetch to the EBU. I am thinking out loud here. At it's core the Committed(F/M) ensure memory operations are atomic and caches don't get into inconsistent states. Once the memory operation is completed the LSU/IFU removes the stall but continues to hold Committed(F/M) because the memory operation has completed and it would be wrong to allow an interrupt to occur with a completed load/store. However this is not true of the IFU. If we lower CommittedF once the operation is complete then this problem is solved. The interrupt won't be masked and the LSU will flush the d cache miss. This requires a minor change in the cachebusfsm and cachefsm. I will report back after I've confirmed this works.
185 lines
11 KiB
Systemverilog
185 lines
11 KiB
Systemverilog
///////////////////////////////////////////
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// dcache (data cache) fsm
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//
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// Written: Ross Thompson ross1728@gmail.com
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// Created: 25 August 2021
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// Modified: 20 January 2023
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//
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// Purpose: Controller for the dcache fsm
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//
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// Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.14 and Table 7.1)
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module cachefsm #(parameter READ_ONLY_CACHE = 0) (
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input logic clk,
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input logic reset,
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// hazard and privilege unit
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input logic Stall, // Stall the cache, preventing new accesses. In-flight access finished but does not return to READY
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input logic FlushStage, // Pipeline flush of second stage (prevent writes and bus operations)
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output logic CacheCommitted, // Cache has started bus operation that shouldn't be interrupted
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output logic CacheStall, // Cache stalls pipeline during multicycle operation
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// inputs from IEU
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input logic [1:0] CacheRW, // [1] Read, [0] Write
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input logic [1:0] CacheAtomic, // Atomic operation
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input logic FlushCache, // Flush all dirty lines back to memory
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input logic InvalidateCache, // Clear all valid bits
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// Bus controls
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input logic CacheBusAck, // Bus operation completed
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output logic [1:0] CacheBusRW, // [1] Read (cache line fetch) or [0] write bus (cache line writeback)
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// performance counter outputs
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output logic CacheMiss, // Cache miss
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output logic CacheAccess, // Cache access
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// cache internals
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input logic CacheHit, // Exactly 1 way hits
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input logic LineDirty, // The selected line and way is dirty
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input logic FlushAdrFlag, // On last set of a cache flush
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input logic FlushWayFlag, // On the last way for any set of a cache flush
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output logic SelAdr, // [0] SRAM reads from NextAdr, [1] SRAM reads from PAdr
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output logic ClearValid, // Clear the valid bit in the selected way and set
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output logic SetValid, // Set the dirty bit in the selected way and set
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output logic ClearDirty, // Clear the dirty bit in the selected way and set
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output logic SetDirty, // Set the dirty bit in the selected way and set
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output logic SelWriteback, // Overrides cached tag check to select a specific way and set for writeback
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output logic LRUWriteEn, // Update the LRU state
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output logic SelFlush, // [0] Use SelAdr, [1] SRAM reads/writes from FlushAdr
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output logic FlushAdrCntEn, // Enable the counter for Flush Adr
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output logic FlushWayCntEn, // Enable the way counter during a flush
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output logic FlushCntRst, // Reset both flush counters
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output logic SelFetchBuffer, // Bypass the SRAM for a load hit by directly using the read data from the ahbcacheinterface's FetchBuffer
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output logic CacheEn // Enable the cache memory arrays. Disable hold read data constant
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);
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logic resetDelay;
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logic AMO, StoreAMO;
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logic AnyUpdateHit, AnyHit;
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logic AnyMiss;
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logic FlushFlag;
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typedef enum logic [3:0]{STATE_READY, // hit states
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// miss states
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STATE_FETCH,
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STATE_WRITEBACK,
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STATE_WRITE_LINE,
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STATE_READ_HOLD, // required for back to back reads. structural hazard on writting SRAM
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// flush cache
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STATE_FLUSH,
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STATE_FLUSH_WRITEBACK} statetype;
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statetype CurrState, NextState;
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assign AMO = CacheAtomic[1] & (&CacheRW);
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assign StoreAMO = AMO | CacheRW[0];
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assign AnyMiss = (StoreAMO | CacheRW[1]) & ~CacheHit & ~InvalidateCache;
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assign AnyUpdateHit = (StoreAMO) & CacheHit;
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assign AnyHit = AnyUpdateHit | (CacheRW[1] & CacheHit);
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assign FlushFlag = FlushAdrFlag & FlushWayFlag;
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// outputs for the performance counters.
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assign CacheAccess = (AMO | CacheRW[1] | CacheRW[0]) & CurrState == STATE_READY;
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assign CacheMiss = CacheAccess & ~CacheHit;
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// special case on reset. When the fsm first exists reset the
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// PCNextF will no longer be pointing to the correct address.
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// But PCF will be the reset vector.
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flop #(1) resetDelayReg(.clk, .d(reset), .q(resetDelay));
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always_ff @(posedge clk)
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if (reset | FlushStage) CurrState <= #1 STATE_READY;
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else CurrState <= #1 NextState;
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always_comb begin
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NextState = STATE_READY;
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case (CurrState)
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STATE_READY: if(InvalidateCache) NextState = STATE_READY;
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else if(FlushCache & ~READ_ONLY_CACHE) NextState = STATE_FLUSH;
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else if(AnyMiss & (READ_ONLY_CACHE | ~LineDirty)) NextState = STATE_FETCH;
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else if(AnyMiss & LineDirty) NextState = STATE_WRITEBACK;
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else NextState = STATE_READY;
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STATE_FETCH: if(CacheBusAck) NextState = STATE_WRITE_LINE;
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else NextState = STATE_FETCH;
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STATE_WRITE_LINE: NextState = STATE_READ_HOLD;
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STATE_READ_HOLD: if(Stall) NextState = STATE_READ_HOLD;
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else NextState = STATE_READY;
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STATE_WRITEBACK: if(CacheBusAck) NextState = STATE_FETCH;
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else NextState = STATE_WRITEBACK;
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// eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack.
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STATE_FLUSH: if(LineDirty) NextState = STATE_FLUSH_WRITEBACK;
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else if (FlushFlag) NextState = STATE_READ_HOLD;
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else NextState = STATE_FLUSH;
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STATE_FLUSH_WRITEBACK: if(CacheBusAck & ~FlushFlag) NextState = STATE_FLUSH;
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else if(CacheBusAck) NextState = STATE_READ_HOLD;
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else NextState = STATE_FLUSH_WRITEBACK;
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default: NextState = STATE_READY;
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endcase
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end
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// com back to CPU
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assign CacheCommitted = (CurrState != STATE_READY) & ~(READ_ONLY_CACHE & CurrState == STATE_READ_HOLD);
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assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss)) |
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(CurrState == STATE_FETCH) |
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(CurrState == STATE_WRITEBACK) |
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(CurrState == STATE_WRITE_LINE) | // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write.
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(CurrState == STATE_FLUSH) |
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(CurrState == STATE_FLUSH_WRITEBACK);
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// write enables internal to cache
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assign SetValid = CurrState == STATE_WRITE_LINE;
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assign SetDirty = (CurrState == STATE_READY & AnyUpdateHit) |
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(CurrState == STATE_WRITE_LINE & (StoreAMO));
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assign ClearValid = '0;
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assign ClearDirty = (CurrState == STATE_WRITE_LINE & ~(StoreAMO)) |
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(CurrState == STATE_FLUSH & LineDirty); // This is wrong in a multicore snoop cache protocal. Dirty must be cleared concurrently and atomically with writeback. For single core cannot clear after writeback on bus ack and change flushadr. Clears the wrong set.
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assign LRUWriteEn = (CurrState == STATE_READY & AnyHit) |
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(CurrState == STATE_WRITE_LINE);
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// Flush and eviction controls
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assign SelWriteback = (CurrState == STATE_WRITEBACK & ~CacheBusAck) |
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(CurrState == STATE_READY & AnyMiss & LineDirty);
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assign SelFlush = (CurrState == STATE_READY & FlushCache) |
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(CurrState == STATE_FLUSH) |
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(CurrState == STATE_FLUSH_WRITEBACK);
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assign FlushAdrCntEn = (CurrState == STATE_FLUSH_WRITEBACK & FlushWayFlag & CacheBusAck) |
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(CurrState == STATE_FLUSH & FlushWayFlag & ~LineDirty);
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assign FlushWayCntEn = (CurrState == STATE_FLUSH & ~LineDirty) |
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(CurrState == STATE_FLUSH_WRITEBACK & CacheBusAck);
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assign FlushCntRst = (CurrState == STATE_FLUSH & FlushFlag & ~LineDirty) |
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(CurrState == STATE_FLUSH_WRITEBACK & FlushFlag & CacheBusAck);
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// Bus interface controls
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assign CacheBusRW[1] = (CurrState == STATE_READY & AnyMiss & ~LineDirty) |
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(CurrState == STATE_FETCH & ~CacheBusAck) |
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(CurrState == STATE_WRITEBACK & CacheBusAck);
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assign CacheBusRW[0] = (CurrState == STATE_READY & AnyMiss & LineDirty) |
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(CurrState == STATE_WRITEBACK & ~CacheBusAck) |
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(CurrState == STATE_FLUSH_WRITEBACK & ~CacheBusAck);
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assign SelAdr = (CurrState == STATE_READY & (StoreAMO | AnyMiss)) | // changes if store delay hazard removed
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(CurrState == STATE_FETCH) |
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(CurrState == STATE_WRITEBACK) |
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(CurrState == STATE_WRITE_LINE) |
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resetDelay;
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assign SelFetchBuffer = CurrState == STATE_WRITE_LINE | CurrState == STATE_READ_HOLD;
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assign CacheEn = (~Stall | FlushCache | AnyMiss) | (CurrState != STATE_READY) | reset | InvalidateCache;
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endmodule // cachefsm
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