cvw/pipelined/src/fpu/fdivsqrt
2022-12-23 00:58:55 -08:00
..
fdivsqrt.sv Removed unused signals from FPU 2022-12-23 00:18:39 -08:00
fdivsqrtfgen2.sv renamed q to u for unified digit selection 2022-09-20 04:35:14 -07:00
fdivsqrtfgen4.sv renamed u to udigit to avoid conflict with U 2022-09-20 19:29:23 -07:00
fdivsqrtfsm.sv Commented out fdiv early termination - broke fsqrt test 2022-12-23 00:58:55 -08:00
fdivsqrtiter.sv Removed unused signals from FPU 2022-12-23 00:18:39 -08:00
fdivsqrtpostproc.sv Revert to 98b824 2022-12-22 23:58:14 -08:00
fdivsqrtpreproc.sv Removed unused signals from FPU 2022-12-23 00:18:39 -08:00
fdivsqrtqsel2.sv Moved swap from qslc to otfc 2022-12-22 15:44:50 +00:00
fdivsqrtqsel4.sv New fdivsqrtqsel4cmp module based on comparators rather than table lookup 2022-10-09 04:47:44 -07:00
fdivsqrtqsel4cmp.sv Moved swap from qslc to otfc 2022-12-22 15:44:50 +00:00
fdivsqrtstage2.sv Moved swap from qslc to otfc 2022-12-22 15:44:50 +00:00
fdivsqrtstage4.sv Moved swap from qslc to otfc 2022-12-22 15:44:50 +00:00
fdivsqrtuotfc2.sv Moved swap from qslc to otfc 2022-12-22 15:44:50 +00:00
fdivsqrtuotfc4.sv Moved swap from qslc to otfc 2022-12-22 15:44:50 +00:00