forked from Github_Repos/cvw
3e916da36e
In the dcache we added a register to save the load read data in the event an itlb miss occurs concurrently with the load in the memory stage. Under this situation we need to record the load ReadDataM into a temporary register, SavedReadDataM. At this time the CPU is stall; however the walker is going to change the address in the dcache which destroys this data. When leaving the PTW_READY state via a walker instruction fault or ITLB write we select this SavedReadDataM so that the CPU can capture it. |
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| .. | ||
| slack-notifier | ||
| wave-dos | ||
| regression-wally.py | ||
| run_sim.sh | ||
| sim-buildroot | ||
| sim-buildroot-batch | ||
| sim-busybear | ||
| sim-busybear-batch | ||
| sim-wally | ||
| sim-wally-batch | ||
| sim-wally-batch-muldiv | ||
| sim-wally-batch-rv32ic | ||
| sim-wally-batch-rv32icfd | ||
| sim-wally-batch-rv64icfd | ||
| sim-wally-muldiv | ||
| sim-wally-rv32ic | ||
| sim-wally-rv32icfd | ||
| sim-wally-rv64icfd | ||
| udiv.c | ||
| wally-buildroot-batch.do | ||
| wally-buildroot.do | ||
| wally-busybear-batch.do | ||
| wally-busybear.do | ||
| wally-coremark_bare.do | ||
| wally-pipelined-batch-muldiv.do | ||
| wally-pipelined-batch-rv32icfd.do | ||
| wally-pipelined-batch-rv64icfd.do | ||
| wally-pipelined-batch.do | ||
| wally-pipelined-muldiv.do | ||
| wally-pipelined-ross.do | ||
| wally-pipelined-rv32icfd.do | ||
| wally-pipelined-rv64icfd.do | ||
| wally-pipelined.do | ||
| wally-privileged.do | ||
| wave-all.do | ||
| wave.do | ||